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? 2012 - 2015 microchip technology inc. ds00001915b-page 1 highlights ? usb-if battery charging 1.1 specification com- pliant ? link power management (lpm) specification compliant ? integrated esd protection circuits - up to 25kv iec air discharge without exter- nal devices ? over-voltage protection circuit (ovp) protects the vbus pin from continuous dc voltages up to 30v ? microchip rapidcharge anywhere? provides: - 3-times the charging current through a usb port over traditional solutions - usb-if battery charging 1.1 compliance to any portable device - charging current up to 1.5amps via compati- ble usb host or dedicated charger - dedicated charging port (dcp), charging (cdp) & standard (sdp) downstream port support ?flexpwr ? technology - extremely low current design ideal for battery powered applications - ?sleep? mode tri-states all ulpi pins and places the part in a low current state - 1.8v to 3.3v io voltage ? single power supply operation - integrated 1.8v regulator - integrated 3.3v regulator - 100mv dropout voltage ? phyboost - programmable usb transceiver drive strength for recovering signal integrity ? varisense tm - programmable usb receiver sensitivity ? ?wrapper-less? design for optimal timing perfor- mance and design ease - low latency hi-speed receiver (43 hi- speed clocks max) al lows use of legacy utmi links with a ulpi bridge ? external reference clock operation available - 19.2mhz reference clock needed - ulpi clock input mode (60mhz sourced by link) - 0 to 3.6v input drive tolerant - able to accept ?noisy? clock sources as refer- ence to internal, low-jitter pll - crystal support available ? smart detection circuits allow identification of usb charger, headset, or data cable insertion ? includes full support for the optional on-the-go (otg) protocol detailed in the on-the-go sup- plement revision 2.0 specification ? supports the otg host negotiation protocol (hnp) and session request protocol (srp) ? uart mode for non-usb serial data transfers ? internal 5v cable short-circuit protection of id, dp and dm lines to vbus or ground ? industrial operating temperature -40 c to +85 c ? 32 pin, qfn rohs compliant package (5 x 5x 0.90 mm height) applications the USB3370 is the solution of choice for any applica- tion where a hi-speed usb connection is desired and when board space, power, and interface pins must be minimized. ? cell phones ?pdas ? mp3 players ? gps personal navigation ? scanners ? external hard drives ? digital still and video cameras ? portable media players ? entertainment devices ? printers ? set top boxes ? video record/playback systems ? ip and video phones ? gaming consoles USB3370 enhanced single supply hi-speed usb ulpi transceiver
USB3370 ds00001915b-page 2 ? 2012 - 2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2012 - 2015 microchip technology inc. ds00001915b-page 3 USB3370 table of contents 1.0 introduction .............................................................................................................. ....................................................................... 4 2.0 USB3370 pin locations and definitions ..................................................................................... .................................................... 6 3.0 limiting values ........................................................................................................... ..................................................................... 9 4.0 electrical characteristics ................................................................................................ ............................................................... 10 5.0 architecture overview ..................................................................................................... .............................................................. 17 6.0 ulpi operation ............................................................................................................ ................................................................. 33 7.0 ulpi register map ......................................................................................................... ............................................................... 51 8.0 application notes ......................................................................................................... ................................................................. 61 9.0 package outline ........................................................................................................... ................................................................. 66 appendix a: data sheet revision history ....................................................................................... .................................................... 71 the microchip web site ........................................................................................................ .............................................................. 72 customer change notification service .......................................................................................... ..................................................... 72 customer support .............................................................................................................. ................................................................. 72 product identification system ................................................................................................. ............................................................ 73
USB3370 ds00001915b-page 4 ? 2012 - 2015 microchip technology inc. 1.0 introduction microchip?s USB3370 is a family of hi-speed usb 2.0 tran sceivers that provide a physical layer (phy) solution well- suited for portable electronic devices. both commercial and industrial temperature applications are supported. several advanced features make the USB3370 the transceiver of choice by reducing both ebom part count and printed circuit board (pcb) area. outstanding esd robustness eliminat es the need for external esd protection devices in typ- ical applications. the internal over-voltage protection circ uit (ovp) protects the USB3370 from voltages up to 30v on the vbus pin. by using a reference clock from the link, the u sb3370 removes the cost of a dedicated crystal reference from the design. the USB3370 includes integrated 3.3v and 1.8v r egulators, making it possible to operate the device from a single power supply. the USB3370 is optimized for use in portable applicati ons where a low operating current and standby currents are essential. the USB3370 operates from a single supply and in cludes integrated regulators for its supplies. the USB3370 also supports the usb link power management protocol (lpm) to further reduce usb operating currents. the USB3370 also includes family is enabled with microchip's rapidcharge anywhere tm which supports usb-if bat- tery charging 1.1 for any portable device. rapidcharge anywhere tm provides three times the charging current through a usb port over traditional solutions which translate up to 1.5amps via compatible usb host or dedicated charger. in addition, this provides a co mplete usb charging ecosystem between device and host port s such as dedicated charging port (dcp), charging (cdp) and st andard (sdp) downstream ports. section 5.9 describes this is further detail. the USB3370 meets all of the electrical requirements for a hi-speed usb host, device, or an on-the-go (otg) trans- ceiver. in addition to the supporting usb signal ing, the USB3370 also provides usb uart mode. USB3370 uses the industry standard utmi+ low pin interface (ulpi) to connect the usb transceiver to the link. ulpi uses a method of in-band signaling and status byte transf ers between the link and phy to facilitate a usb session with only twelve pins. the USB3370 uses microchip?s ?wrapper-less? technology to im plement the ulpi interface. this ?wrapper-less? tech- nology allows the phy to achieve a low latency transmit and receive time. microchip?s low latency transceiver allows an existing utmi link to be reused by adding a utmi to ul pi bridge. by adding a bridge to the asic the existing and proven utmi link ip can be reused.
? 2012 - 2015 microchip technology inc. ds00001915b-page 5 USB3370 the USB3370 includes an integrated 3.3v ldo regulator that is used to generate 3.3v from power applied to the vbat pin. the voltage on the vbat pin can range from 3.0 to 5.5v. the regulator dropout voltage is less than 100mv which allows the phy to continue usb signaling when the voltage on vbat drops to 3.0v. the usb transceiver will continue to operate at lower voltages, although some parameters may be outside the limits of the usb specifications. the vbat and vdd33 pins should never be connected together. in usb uart mode, the USB3370 dp and dm pins are redefined to enable pass-through of asynchronous serial data. the USB3370 will enter uart mode when programmed, as described in section 6.7.1 . 1.1 reference documents utmi+ low pin interface (ulpi) specification, rev. 1.1 universal serial bus spec ification, revision 2.0 on-the-go supplement to the usb2.0 specification, rev. 1.3 on-the-go supplement to the usb2.0 specification, rev. 2.0 usb battery charging specification, rev. 1.1 figure 1-1: block diagram USB3370 otg hi-speed usb transceiver ulpi interface ulpi registers and state machine bias low jitter integrated pll integrated power management vbus id dp dm rbias esd protection refclk / xi data[7:0] resetb vdd18 vdd33 vbat dir nxt stp clkout ovp vddio xo cpen_n bc 1.1 extvbus
USB3370 ds00001915b-page 6 ? 2012 - 2015 microchip technology inc. 2.0 USB3370 pin location s and definitions 2.1 USB3370 pin locations and descriptions 2.1.1 USB3370 pin diagra m and pin definitions the illustration below is viewed from the top of the package. the following table details the pin definitions for the figure above. figure 2-1: USB3370 pin locations - top view table 2-1: USB3370 pin descriptions pin name direction/ type active level description 27 clkout output, cmos n/a ulpi clock out mode: 60mhz ulpi clock output. all ulpi signals are driven synchronous to the rising edge of this clock. ulpi clock in mode: connect this pin to vddio to configure 60mhz ulpi clock in mode as described in section 5.5.1 . 21 nxt output, cmos high the phy asserts nxt to throttle the data. when the link is sending data to the phy, nxt indicates when the current byte has been accepted by the phy. 1 data[0] i/o, cmos n/a ulpi bi-directional data bus. data[0] is the lsb. 32 data[1] i/o, cmos n/a ulpi bi-directional data bus. 31 data[2] i/o, cmos n/a ulpi bi-directional data bus. usb3300 hi-speed usb2 ulpi phy 32 pin qfn 1 2 3 4 5 6 7 8 32 pin qfn 5x5 mm gnd flag 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vddio rbias dp extvbus dm data0 vddio data7 stp dir vdd18 nxt id nc vbus nc data1 gnd vdd33 vbat cpen_n refclk xo resetb data2 nc data6 vddio data4 clkout data3 data5
? 2012 - 2015 microchip technology inc. ds00001915b-page 7 USB3370 28 data[3] i/o, cmos n/a ulpi bi-directional data bus. 26 data[4] i/o, cmos n/a ulpi bi-directional data bus. 6 extvbus input, cmos high external vbus detect. connect to fault output of an external usb power switch or an external vbus valid comparator. see section 5.7.5, "external vbus indicator," on page 29 for details. this pin has a pull down resistor to prevent it from floating when the ulpi bit useexternalvbusindicator is set to 0. 25 data[5] i/o, cmos n/a ulpi bi-directional data bus. 24 data[6] i/o, cmos n/a ulpi bi-directional data bus. 9 10 29 nc n/a n/a no connect. leave pin floating. 23 data[7] i/o, cmos n/a ulpi bi-directional data bus. data[7] is the msb. 12 cpen_n output, open drain low external 5 volt supply enable. this pin is used to enable the external vbus power supply. the cpen_n pin is tri-stated on por. 5dp i/o, analog n/a d+ pin of the usb cable. 4dm i/o, analog n/a d- pin of the usb cable. 14 vdd33 power n/a 3.3v regulator output. a 1.0uf (<1 ohm esr) bypass capacitor to ground is required for regulator stability. the bypass capacitor should be placed as close as possible to the USB3370. 11 vbat power n/a regulator input. the regulator supply can be from 5.5v to 3.0v. 13 vbus i/o, analog n/a this pin is used for the vbus comparator inputs and for vbus pulsing during session request protocol. an external resistor, r vbus , is required between this pin and the usb connector. 7id input, analog n/a for device applications the id pin is connected to vdd33 . for host applications id is grounded. for otg applications the id pin is connected to the usb connector. 3 rbias analog, cmos n/a bias resistor pin. this pin requires an 10k ? (1%) resistor to ground, placed as close as possible to the USB3370. nominal voltage during ulpi operation is 0.8v. 16 xo output, analog n/a crystal pin. if using an external clock on xi this pin should be floated. 15 refclk input, cmos n/a ulpi clock out mode: reference clock or xi (crystal in) pin. ulpi clock in mode: 60mhz ulpi clock input. table 2-1: USB3370 pin descriptions (continued) pin name direction/ type active level description
USB3370 ds00001915b-page 8 ? 2012 - 2015 microchip technology inc. 17 resetb input, cmos, low when low, the part is suspended and the 3.3v and 1.8v regulators are disabled. when high, the USB3370 will operate as a normal ulpi device, as described in section 5.6.2 . the state of this pin may be changed asynchronously to the clock signals. when asserted for a minimum of 1 microsecond and then de-asserted, the ulpi r egisters are reset to their default state and all internal state machines are reset. 18 vdd18 power n/a 1.8v regulator output. a 1.0uf (<1 ohm esr) bypass capacitor to ground is required for regulator stability. the bypass capacitor should be placed as close as possible to the USB3370. 20 stp input, cmos high the link asserts stp for one clock cycle to stop the data stream currently on the bus. if the link is sending data to the phy, stp indicates the last byte of data was on the bus in the previous cycle. 19 dir output, cmos n/a controls the direction of the data bus. when the phy has data to transfer to the link, it drives dir high to take ownership of the bus. when the phy has no data to transfer it drives dir low and monitors the bus for commands from the link. 2 22 30 vddio power n/a 1.8v to 3.3v ulpi interface supply voltage. flag 8 gnd ground n/a ground. table 2-1: USB3370 pin descriptions (continued) pin name direction/ type active level description
? 2012 - 2015 microchip technology inc. ds00001915b-page 9 USB3370 3.0 limiting values 3.1 absolute maximum ratings 3.2 recommended operating conditions table 3-1: absolute maximum ratings parameter symbol conditions min typ max units vbus , vbat , and id , voltage to gnd v max_usb voltage measured at pin. vbus tolerant to 30v with external r vbus . -0.5 6.0 v dp and dm voltage to gnd v max_dpdm -0.5 5.0 v maximum vdd18 voltage to ground v max_18v -0.5 2.5 v maximum vdd33 voltage to ground v max_33v -0.5 4.0 v maximum vddio voltage to ground v max_iov -0.5 4.0 maximum i/o voltage to ground v max_in -0.5 v ddio + 0.7 maximum i/o voltage to ground ( extvbus , cpen_n ) v max_in -0.5 5.5v operating temperature t max_op -40 85 c storage temperature t max_stg -55 150 c note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 3-2: recommended operating conditions parameter symbol conditions min typ max units vbat to gnd v bat 3.0 5.5 v vdd33 to gnd v dd33 3.0 3.3 3.6 v vdd18 to gnd v dd18 1.6 1.8 2.0 v vddio to gnd v ddio 1.6 1.8-3.3 3.6 v input voltage on digital pins ( resetb , stp , dir , nxt , data[7:0] ) v i 0.0 v ddio v input voltage on digital pins ( extvbus, cpen_n ) v i 0.0 5.0 v voltage on analog i/o pins ( dp , dm , id ) v i(i/o) 0.0 v dd33 v vbus to gnd v vmax 0.0 5.5 ambient temperature t a -40 85 c
USB3370 ds00001915b-page 10 ? 2012 - 2015 microchip technology inc. 4.0 electrical characteristics the following conditions are a ssumed unless otherwise specified: v dd33 = 3.0 to 3.6v; vdd18 = 1.6 to 2.0v; v ss = 0v; t a = -40c to +85c 4.1 operating current note 4-1 clocksuspendm bit = 0. note 4-2 sessend, vbusvld, and idfloat comparators disabled. stp interface protection disabled. note 4-3 refclk is off 4.2 clock specifications the model number for each frequency of refclk is provided in product identificatio n system on page 73 . note 1: t start and t prep are measured from the time when refclk and resetb are both valid to when the USB3370 de-asserts dir . 2: the USB3370 uses the autoresume feature, section 6.4.1.4 , to allow a host start-up time of less than 1ms. note 4-4 refclk with oscillator input note 4-5 crystal input table 4-1: operating current parameter symbol conditions min typ max units synchronous mode current (default configuration) i vbat(sync) usb idle 24 27 29 ma i vio(sync) 237ma synchronous mode current (hs usb operation) i vbat(hs) active usb transfer 33 35 37 ma i vio(hs) 5614ma synchronous mode current (fs/ls usb operation) i vbat(fs) active usb transfer 25 28.5 30 ma i vio(fs) 4513ma serial mode current (fs/ls usb) note 4-1 i vbat(fs_s) 789ma i vio(fs_s) 00.10.7ma usb uart current note 4-1 i vbat(uart) 789ma i vio(uart) 00.10.7ma low power mode note 4-2 note 4-3 i vbat(suspend) v vbat = 4.2v v vddio = 1.8v 29 32 83 ua i vio(suspend) 002ua reset mode note 4-3 i vbat(rstb) resetb = 0 v vbat = 4.2v v vddio = 1.8v 0.1 1 12 ua i vio(rstb) 007ua table 4-2: clock specifications parameter symbol conditions min typ max units suspend recovery time t start lpm enable = 0 1.0 1.1 1.32 ms t start_lpm lpm enable = 1 125 150 us phy preparation time 60mhz refclk t prep lpm enable = 0 1.0 1.1 1.32 ms t prep_lpm lpm enable = 1 125 150 us clkout duty cycle dc clkout ulpi clock input mode 45 55 % refclk duty cycle dc refclk 20 80 % refclk frequency accuracy f refclk -500 +500 ppm
? 2012 - 2015 microchip technology inc. ds00001915b-page 11 USB3370 4.3 ulpi interface timing note 4-6 refclk does not need to be aligned in any way to the ulpi signals. 4.4 digital io pins table 4-3: ulpi interface timing parameter symbol conditions min max units 60mhz ulpi output clock note 4-6 setup time ( stp , data in) t sc , t sd model-specific refclk 5.0 ns hold time ( stp , data in) t hc , t hd model-specific refclk 0.0 ns output delay (control out, 8-bit data out) t dc , t dd model-specific refclk 1.5 6 ns 60mhz ulpi input clock setup time ( stp , data in) t sc , t sd 60mhz refclk 3ns hold time ( stp , data in) t hc , t hd 60mhz refclk 0ns output delay (control out, 8-bit data out) t dc , t dd 60mhz refclk 0.5 6.0 ns note: c load = 10pf. table 4-4: digital io characteristics: resetb, stp, dir, nxt, data[7:0], and refclk pins parameter symbol conditions min typ max units low-level input voltage v il v ss 0.8 v high-level input voltage v ih 0.68 * v ddio v ddio v high-level input voltage refclk and resetb v ih_ref 0.68 * v ddio v dd33 v low-level output voltage v ol i ol = 8ma 0.4 v high-level output voltage v oh i oh = -8ma v ddio - 0.4 v output rise time t iorise c load = 10pf 1.19 ns output fall time t iofall c load = 10pf 1.56 ns input leakage current i li 10 ua pin capacitance cpin 4 pf stp pull-up resistance r stp interfaceprotectdisable = 0 55 67 80 k ? data[7:0] pull-down resistance r data_pd ulpi synchronous mode 55 67 77 k ? clkout external drive v ih_ed at start-up or following reset 0.4 * v ddio v
USB3370 ds00001915b-page 12 ? 2012 - 2015 microchip technology inc. 4.5 dc characteristics: analog i/o pins table 4-5: dc characteristics: analog i/o pins (dp/dm) parameter symbol conditions min typ max units ls/fs functionality input levels differential receiver input sensitivity v difs | v(dp) - v(dm) | 0.2 v differential receiver common-mode voltage v cmfs 0.8 2.5 v single-ended receiver low level input voltage v ilse note 4-8 0.8 v single-ended receiver high level input voltage v ihse note 4-8 2.0 v single-ended receiver hysteresis v hysse 0.050 0.150 v output levels low level output voltage v fsol pull-up resistor on dp; r l = 1.5k ? to v dd33 0.3 v high level output voltage v fsoh pull-down resistor on dp, dm; note 4-8 r l = 15k ? to gnd 2.8 3.6 v termination driver output impedance for hs z hsdrv steady state drive 40.5 45 49.5 ? input impedance z inp rx, rpu, rpd disabled 1.0 m ? pull-up resistor impedance r pu bus idle, note 4-7 0.900 1.24 1.575 k ? pull-up resistor impedance r pu device receiving, note 4-7 1.425 2.26 3.09 k ? pull-dn resistor impedance r pd note 4-7 14.25 16.9 20 k ? hs functionality input levels hs differential in put sensitivity v dihs | v(dp) - v(dm) | 100 mv hs data signaling common mode voltage range v cmhs -50 500 mv hs squelch detection threshold (differential) v hssq varisense[1:0] = 00b note 4-9 100 150 mv hs disconnect threshold v hsdsc 525 625 mv output levels high speed low level output voltage (dp/dm referenced to gnd) v hsol 45 ? load -10 10 mv high speed high level output voltage (dp/dm referenced to gnd) v hsoh 45 ? load 360 440 mv high speed idle level output voltage (dp/dm referenced to gnd) v olhs 45 ? load -10 10 mv chirp-j output voltage (differential) v chirpj hs termination resistor disabled, pull-up resistor connected. 45 ? load. 700 1100 mv chirp-k output voltage (differential) v chirpk hs termination resistor disabled, pull-up resistor connected. 45 ? load. -900 -500 mv
? 2012 - 2015 microchip technology inc. ds00001915b-page 13 USB3370 note 4-7 the resistor value follows the 27% re sistor ecn published by the usb-if. note 4-8 the values shown are valid when the usb regoutput bits in the usb io & power management register are set to the default value. note 4-9 an automatic waiver up to 200mv is granted to accommodate system-level elements such as measurement/test fixtures, capt ive cables, emi components, and esd suppression. this parameter can be tuned using varisense technology, as defined in section 7.1.3.1 of section 7.0, "ulpi register map" . 4.6 dynamic characteristics: analog i/o pins leakage current off-state leakage current i lz 10 ua port capacitance transceiver input capacitance c in pin to gnd 5 10 pf table 4-6: dynamic characteristics: analog i/o pins (dp/dm) parameter symbol conditions min typ max units fs output driver timing fs rise time t fr c l = 50pf; 10 to 90% of |v oh - v ol | 420ns fs fall time t ff c l = 50pf; 10 to 90% of |v oh - v ol | 420ns output signal crossover voltage v crs excluding the first transition from idle state 1.3 2.0 v differential rise/fall time matching t frfm excluding the first transition from idle state 90 111.1 % ls output driver timing ls rise time t lr c l = 50-600pf; 10 to 90% of |v oh - v ol | 75 300 ns ls fall time t lf c l = 50-600pf; 10 to 90% of |v oh - v ol | 75 300 ns differential rise/fall time matching t lrfm excluding the first transition from idle state 80 125 % hs output driver timing differential rise time t hsr 500 ps differential fall time t hsf 500 ps driver waveform requirements eye pattern of template 1 in usb 2.0 specification high speed mode timing receiver waveform requirements eye pattern of template 4 in usb 2.0 specification data source jitter and receiver jitter tolerance eye pattern of template 4 in usb 2.0 specification table 4-5: dc characteristics: analog i/o pins (dp/dm) (continued) parameter symbol conditions min typ max units
USB3370 ds00001915b-page 14 ? 2012 - 2015 microchip technology inc. 4.7 vbus electrical characteristics note 4-10 the r vpd and r vpu values include the required 1k ? external r vbus resistor. 4.8 id electrical characteristics 4.9 usb charger detection characteristics table 4-7: vbus electrical characteristics parameter symbol conditions min typ max units sessend trip point v sessend 0.2 0.5 0.8 v sessvld trip point v sessvld 0.8 1.4 2.0 v vbusvld trip point v vbusvld 4.4 4.58 4.75 v vbus pull-up r vpu vbus to vdd33 note 4-10 ( chargevbus = 1) 1.29 1.34 1.45 k ? vbus pull-down r vpd vbus to gnd note 4-10 ( dischargevbus = 1) 1.55 1.7 1.85 k ? vbus impedance r vb vbus to gnd 40 75 100 k ? a-device impedance to ground r idgnd maximum impedance to ground on id pin 100 k ? table 4-8: id electrical characteristics parameter symbol conditions min typ max units id ground trip point v idgnd 0.4 0.7 0.9 v id float trip point v idfloat 1.6 2.2 2.5 v id pull-up resistance r id idpullup = 1 80 100 120 k ? id weak pull-up resistance r idw idpullup = 0 1 m ? id pull-dn resistance r idpd idgnddrv = 1 1000 ? table 4-9: usb charger detection characteristics parameter symbol conditions min typ max units data source voltage v dat_src i dat_src < 250ua 0.5 0.7 v data detect voltage v dat_ref 0.25 0.4 v data source current i dat_src 250 ua data sink current i dat_sink 50 150 ua data connect current i dp_src 713ua weak pull-up resistor impedance r cd configured by bits 4 and 5 in usb io & power management register. 128 170 212 k ?
? 2012 - 2015 microchip technology inc. ds00001915b-page 15 USB3370 4.10 regulator output voltages and capacitor requirement 4.11 piezoelectric resonator for internal oscillator the internal oscillator may be used with an external quartz crystal or ceramic resonator as described in section 5.4 . see table 4-11 for the recommended crystal specifications. note 4-11 the required bit rate accuracy for hi-speed usb app lications is 500 ppm as provided in the usb 2.0 specification. this takes into account th e effect of voltage, temperature, aging, etc. note 4-12 this number includes the pad, the bond wire and the lead frame. printed circuit board (pcb) capacitance is not included in this value. the pcb capacitance value and the capacitance value of the xo and refclk pins are required to accurately calculate the value of the two external load capacitors. note 4-13 refer to section 5.4 and figure 8-1 for more information. table 4-10: regulator output voltages and capacitor requirement parameter symbol conditions min typ max units regulator output voltage v dd33 5.5v > vbat > 3.0v 2.8 3.3 3.6 v usb uart mode & uart regoutput[1:0] = 01 6v > vbat > 3.0v 2.7 3.0 3.3 v usb uart mode & uart regoutput[1:0] = 10 6v > vbat > 3.0v 2.47 2.75 3.03 v usb uart mode & uart regoutput[1:0] = 11 6v > vbat > 3.0v 2.25 2.5 2.75 v regulator bypass capacitor c out33 1.0 uf bypass capacitor esr c esr33 1 ? regulator output voltage v dd18 3.6v > vdd33 > 2.25v 1.6 1.8 2.0 v regulator bypass capacitor c out18 1.0 uf bypass capacitor esr c esr18 1 ? table 4-11: USB3370 quartz crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund -see product identification system on page 73 -mhz total allowable ppm budget - - 500 ppm note 4-11 shunt capacitance c o -7 typ-pf load capacitance c l - 20 typ - pf drive level p w 0.1 - - mw equivalent series resistance r 1 --30ohm USB3370 refclk pin capacitance -3 typ-pf note 4-12 USB3370 xo pin capacitance - 3 typ - pf note 4-12 recommended resistance between xi and xo 1m - - ohm note 4-13
USB3370 ds00001915b-page 16 ? 2012 - 2015 microchip technology inc. 4.12 esd and latch-up performance note 4-14 refclk , xo , id, and resetb pins: 5kv human body model. table 4-12: esd and latch-up performance parameter conditions min typ max units comments esd performance note 4-14 human body model 8 kv device system en/iec 61000-4-2 contact discharge 25 kv 3rd party system test system en/iec 61000-4-2 air-gap discharge 25 kv 3rd party system test latch-up performance all pins eia/jesd 78, class ii 150 ma
? 2012 - 2015 microchip technology inc. ds00001915b-page 17 USB3370 5.0 architecture overview the USB3370 consists of the blocks shown in the diagram below. 5.1 ulpi digital operation and interface this section of the USB3370 is covered in detail in section 6.0, "ulpi operation" . 5.2 usb 2.0 hi-speed transceiver the blocks in the lower left-hand corner of figure 6-1 interface to the dp/dm pins. 5.2.1 usb transceiver the USB3370 transceiver includes a universal serial bus spec ification rev 2.0 compliant receiver and transmitter. the dp/dm signals in the usb cable connect directly to the receivers and transmitters. the receiver consists of receivers for hs and fs/ls mode . depending on the mode, the se lected receiver provides the serial data stream through the multiplexer to the rx logic block. for hs mode support, the hs rx block contains a squelch circuit to insure that noise is not interpreted as data. the rx block also includes a single-ended receiver on each of the data lines to determine the correct fs linestate. data from the link is encoded, bit st uffed, serialized and transmitted onto t he usb cable by the transmitter. separate differential fs/ls and hs transmitte rs are included to support all modes. the USB3370 tx block meets the hs signaling level requir ements in the usb 2.0 spec ification when the pcb traces from the dp and dm pins to the usb connector are correctly designed. in some systems the pr oper 90 ohm differential impedance can not be maintained and it may be desirable to compensate for loss by adjusting the hs transmitter ampli- tude and this hs squelch threshold. the phyboost bits in the hs compensation register may be configured to adjust the hs transmitter amplitude at the dp and dm pins. the varisense bits in the hs compensation register can also be used to lower the squelch threshold to compensate for losses on the pcb. to ensure proper operation of the usb transceiver the settings of ta b l e 5 - 1 must be followed. figure 5-1: USB3370 system diagram bias integrated low jitter pll rbias esd protection r cd r cd r pd r pd r pu r pu r id r idw r vpu r vb dir nxt stp clkout data7 data6 data5 data4 data3 data2 data0 data1 refclk / xi vddio vbat vdd33 vbus ldo dp dm id ulpi digitial digital io otg module tx rx hs/fs/ls tx encoding hs/fs/ls rx decoding resetb tx data rx data idgnd idfloat rid value sessend sessvalid vbusvalid r vpd ovp xo cpen_n vdd33 vdd33 vdd33 ldo vdd18 extvbus
USB3370 ds00001915b-page 18 ? 2012 - 2015 microchip technology inc. 5.2.2 termination resistors the USB3370 transceiver fully integrates all of the usb termination resistors on both dp and dm . this includes 1.5k ? pull-up resistors, 15k ? pull-down resistors and the 45 ? high speed termination resistors. these resistors require no tuning or trimming by the link. the st ate of the resistors is determined by th e operating mode of the transceiver when operating in synchronous mode. the xcvrselect[1:0] , termselect and opmode[1:0] bits in the function control register, and the dppulldown and dmpulldown bits in the otg control register control the configuration of th e termination resistors. all possible valid resistor combinations are shown in ta b l e 5 - 1 , and operation is ensured in only the configurations shown. if a ulpi reg- ister setting is configured that does not match a setting in the table, the transce iver operation is not guaranteed and the settings in the last row of table 5-1 will be used. ? rpu_dp_en activates the 1.5k ? dp pull-up resistor ? rpu_dm_en activates the 1.5k ? dm pull-up resistor ? rpd_dp_en activates the 15k ? dp pull-down resistor ? rpd_dm_en activates the 15k ? dm pull-down resistor ? hsterm_en activates the 45 ? dp and dm high speed termination resistors table 5-1: dp/dm termination vs. signaling mode signaling mode ulpi register settings USB3370 termination resistor settings xcvrselect[1:0] termselect opmode[1:0] dppulldown dmpulldown rpu_dp_en rpu_dm_en rpd_dp_en rpd_dm_en hsterm_en general settings tri-state drivers, note 5-1 xxbxb01bxbxb0b0b0b0b0b power-up or vbus < v sessend 01b0b00b1b1b0b0b1b1b0b host settings host chirp 00b0b10b1b1b0b0b1b1b1b host high speed 00b 0b 00b 1b 1b 0b 0b 1b 1b 1b host full speed x1b1b00b1b1b0b0b1b1b0b host hs/fs suspend 01b1b00b1b1b0b0b1b1b0b host hs/fs resume 01b1b10b1b1b0b0b1b1b0b host low speed 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b host ls suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b host ls resume 10b1b10b1b1b0b0b1b1b0b host test j/test_k 00b0b10b1b1b0b0b1b1b1b peripheral settings peripheral chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b peripheral hs 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b peripheral fs 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b peripheral hs/fs suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b peripheral hs/fs resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b peripheral ls 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b peripheral ls suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b peripheral ls resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b peripheral test j/test k 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b otg device, peripheral chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hs 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b
? 2012 - 2015 microchip technology inc. ds00001915b-page 19 USB3370 note 1: this is equivalent to table 40, sect ion 4.4 of the ulpi 1.1 specification. 2: USB3370 does not support operation as an upstream hub port. see section 6.4.1.3 . note 5-1 when resetb = 0 the hs termination will tri-state the usb drivers note 5-2 the transceiver operation is not guarante ed in a combination that is not defined. the USB3370 uses the 27% resistor ecn resistor tolerances. the resistor values are shown in table 4-5 . 5.3 bias generator this block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the analog circuits. this block requires an external 10k , 1% tolerance, reference resistor connected from rbias to ground. this resistor should be placed as close as possibl e to the USB3370 to minimize the trace length. the nominal voltage at rbias is 0.8v +/- 10% and therefore the resistor will dissipate approximately 80 w of power. 5.4 crystal reference support the USB3370 provides support for a crystal to provide the re ference frequency required by the device in place of a clock oscillator. the crystal should be connected to the refclk/xi and xo pins. if a clock oscillator is used in place of a crystal, it should be driven into the re fclk/xi pin, and the xo pin should be le ft floating. proper care should be taken to ensure that a crystal is selected with ap propriate power dissipation characteristics. 5.5 integrated low jitter pll the USB3370 uses an integrated low ji tter phase locked loop (pll) to provide a clean 480mhz clock required for hs usb signal quality. this clock is used by the phy during bot h transmit and receive. the USB3370 pll requires an accu- rate frequency reference to be driven on the refclk pin. 5.5.1 refclk frequency selection the USB3370 pll is designed to operate in one of two reference clock modes. in the first mode, the 60mhz ulpi clock is driven on the refclk pin. in the second mode a reference clock is driven on the refclk pin. the link is driving the ulpi clock, in the first mode, and this is referred to as ulpi clock input mode . in the second mode, the USB3370 generates the ulpi clock, and this is referred to as ulpi clock output mode . during start-up, the USB3370 monitors the clkout pin. if a connection to vddio is detected, the USB3370 is config- ured for a 60mhz ulpi reference clock driven on the refclk pin. section 5.5.1.1 and section 5.5.1.2 describe how to configure the USB3370 for either ulpi cl ock input mode or ulpi clock output mode. otg device, peripheral fs 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hs/fs suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hs/fs resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral test j/test k 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b charger detection connect detect 01b0b00b0b1b0b0b0b1b0b any combination not defined above, note 5- 2 0b 0b 1b 1b 0b table 5-1: dp/dm termination vs. signaling mode (continued) signaling mode ulpi register settings USB3370 termination resistor settings xcvrselect[1:0] termselect opmode[1:0] dppulldown dmpulldown rpu_dp_en rpu_dm_en rpd_dp_en rpd_dm_en hsterm_en
USB3370 ds00001915b-page 20 ? 2012 - 2015 microchip technology inc. 5.5.1.1 ulpi clock input mode (60mhz refclk mode) when using ulpi clock input mode, the link must supply the 60mhz ulpi cloc k to the USB3370. in this mode the 60mhz ulpi clock is connected to the refclk pin, and the clkout pin is tied high to vddio . after the pll has locked to the correct frequency, the USB3370 will de-assert dir and the link can begin using the ulpi interface. the USB3370 is ensured to start the clock within the time specified in table 4-2 . for host applications, the ulpi autoresume bit should be enabled. this is described in section 6.4.1.4 . for the USB3370, the ref pins should be tied to ground. 5.5.1.2 ulpi clock output mode when using ulpi clock output mode, the USB3370 generates the 60mhz ulpi clock used by the link. in this mode, the refclk pin must be driven with the model-specific frequency, and the clkout pin sources the 60mhz ulpi clock to the link. when using ulpi clock out put mode, the system must not drive the clkout pin following por or hard- ware reset with a voltage that exceeds the value of v ih_ed provided in ta b l e 4 - 3 . an example of ulpi clock output mode is shown in figure 8-1 after the pll has locked to the correct frequency, the USB3370 generates the 60mhz ulpi clock on the clkout pin, and de-asserts dir to indicate that the pll is locked. the USB3370 is ensured to start the clock within the time specified in ta b l e 4 - 2 , and it will be accurate to within 50 0ppm. for host applications the ulpi autoresume bit should be enabled. this is described in section 6.4.1.4 . when using ulpi clock output mode, the edges of the refer ence clock do not need to be aligned in any way to the ulpi interface signals. there is no need to align the phase of the refclk and the clkout . figure 5-2: configuring the USB3370 for ulpi clock input mode (60 mhz) clkout refclk ~ ~ ~ ~ phy clock source to pll link ulpi clk out reference clk in vdd18/ vddio
? 2012 - 2015 microchip technology inc. ds00001915b-page 21 USB3370 5.5.2 refclk amplitude the reference clock should be connected to the refclk pin as shown in the application diagrams, figure 8-1 . the refclk pin is designed to be driven with a square wave from 0v to vddio , but can be driven with a square wave from 0v to as high as 3.6v. the USB3370 uses only the positive edge of the refclk . if a digital reference is not available, the refclk pin can be driven by an analog sine wave that is ac coupled into the refclk pin. if using an analog clock the dc bias should be set at the mid-point of the vdd18 supply using a bias circuit as shown in figure 5-4 . the amplitude must be greater than 300mv peak to peak. the component values pro- vided in figure 5-4 are for example only. the actual values shoul d be selected to satisfy system requirements. the refclk amplitude must comply with t he signal amplitudes shown in ta b l e 4 - 4 and the duty cycle in ta b l e 4 - 2 . 5.5.3 refclk jitter the USB3370 is tolerant to jitter on the reference clock. the refclk jitter should be limited to a peak to peak jitter of less than 1ns over a 10us time interval. if this level of jitter is exceeded when config ured for either ulpi clock input mode or ulpi clock output mode, the usb337 0 high speed eye diagram may be degraded. the frequency accuracy of the refclk must me et the +/- 500ppm requirement as shown in ta b l e 4 - 2 . figure 5-3: configuring the usb3 370 for ulpi clock output mode figure 5-4: example of circuit used to shift a reference clock common- mode voltage level clkout refclk ~ ~ ~ ~ phy from pll clock source to pll link ulpi clk in clock 47k 47k 0.1uf 1.8v supply to refclk pin
USB3370 ds00001915b-page 22 ? 2012 - 2015 microchip technology inc. 5.5.4 refclk enable/disable the refclk should be enabled when the resetb pin is brought high. the ulpi in terface will start running after the time specified in ta b l e 4 - 2 . if the reference clock enable is delayed relative to the resetb pin, the ulpi interface will start operation delayed by the same amount. th e reference clock can be run at anytime the resetb pin is low without causing the USB3370 to start-up or draw current. when the USB3370 is placed in low power mode or carkit mode, the reference clock can be stopped after the final ulpi register write is complete. the stp pin is asserted to bring the USB3370 out of low power mode. the reference clock should be started at the same time stp is asserted to minimize the USB3370 start-up time. if the reference clock is stopped while in ulpi synchronous mode the pll will come out of lock and the frequency of oscillation will decrease to the minimum allowed by the p ll design. if the reference clock is stopped during a usb ses- sion, the session may drop. 5.6 internal regulators and por the USB3370 includes integrated power management functions, including a low- dropout regulator that can be used to generate the 3.3v usb supply, an integrated 1.8v regulator, and a por generator described in section 5.6.2 . 5.6.1 integrated low dropout regulators the USB3370 includes two integrated linear regulators. power sourced at the vbat pin is regulated to 3.3v and 1.8v output on the vdd33 and vdd18 pins. to ensure stability, both regulators require an external bypass capacitor as spec- ified in ta b l e 4 - 1 0 placed as close to the pin as possible. the USB3370 regulators are designed to generate the 3.3 vo lt and 1.8 volt supplies for the USB3370 only. using the regulators to provide current for other circuits is not recommended and microchip does not guarantee usb performance or regulator stability. during usb uart mode the 3.3v regulator output voltage can be changed to allow the USB3370 to work with uarts operating at different operating voltages. the 3.3v re gulator output is configured to the voltages shown in table 4-10 with the uart regoutput[1:0] bits in the usb io & power management register. the regulators are enabled by the resetb pin. when resetb pin is low both regulators are disabled and the regulator outputs are pulled low by weak pull-down. the resetb pin must be brought high to enable the regulators. for peripheral-only or host-only bus-powered applications, the input to vbat may be derived from the vbus pin of the usb connector. in this configuration, the supply must be capable of withstanding any transient voltage present at the vbus pin of the usb connector. microchip does not recommend connecting the vbat pin to the vbus terminal of the usb connector. 5.6.2 power on reset (por) the USB3370 provides a por circuit that g enerates an internal reset pulse after the vdd18 supply is stable. after the internal por goes high the USB3370 will release from reset and begin normal ulpi operation as described in section 5.6.4 . the ulpi registers will power up in their default state summarized in ta b l e 7 - 1 when the 1.8v supply comes up. cycling the resetb pin can also be used to reset the ulpi registers to t heir default state (and reset all internal state machines) by bringing the pin low for a minimum of 1 microsecond and then high. it is not necessary to wait for the vdd33 and vdd18 pins to discharge to 0 volts to reset the part. the resetb pin must be pulled high to enable the 3.3v and 1.8v re gulators. a pull-down resistor is not present on the resetb pin and therefore the system should drive the resetb pin to the desired state at all times. if the system does not need to place the USB3370 into reset mode the resetb pin can be connected to a supply between 1.8v and 3.3v. 5.6.3 recommended power supply sequence for usb operation, the USB3370 requires a valid voltage on the vbat and vddio pins. the vdd33 and vdd18 reg- ulators are automatically enabled when the resetb pin is brought high. for the usb3343, table 5-2 presents the power supply configurations in more detail. the resetb pin can be held low until the vbat supply is stable. if the link is no t ready to interface the USB3370, the link may choose to hold the resetb pin low until it is ready to control the ulpi interface.
? 2012 - 2015 microchip technology inc. ds00001915b-page 23 USB3370 note 5-3 vddio must be present for ulpi pins to tri-state. 5.6.4 start-up the power on default state of the USB3370 is ulpi sy nchronous mode. the USB3370 requires the following conditions to begin operation: the power supplies must be stable, the refclk must be present and the resetb pin must be high. after these conditions are met, the USB3370 will begin ulpi operation that is described in section 6.0 . figure 5-5 below shows a timing diagram to illustrate the star t-up of the USB3370. at t0, the supplies are stable and the USB3370 is held in reset mode. at t1, the link drives resetb high after the refclk has started. the resetb pin may be brought high asynchronously to refclk . once, the 3.3v and 1.8v internal supplies become stable the USB3370 will apply the 15kohm pull downs to the data bus and assert dir until the internal pll has locked. after the pll has locked, the USB3370 will ch eck that the link has de-asserted stp and at t2 it will de-assert dir and begin ulpi operation. the ulpi bus will be available as shown in figure 5-5 in the time defined as t start given in table 4-2 . if the refclk signal starts after the resetb pin is brought high, then time t0 will begin when refclk starts. t start also assumes that the link has de-asserted stp . if the link has held stp high the USB3370 will hold dir high until stp is de- asserted. when the link de-asserts stp , it must be ready drive the ulpi data bus to idle (00h) for a minimum of one clock cycle after dir de-asserts. table 5-2: operating mode vs. power supply configuration vbat vddio resetb operati ng modes available 0 0 0 powered off 1 x 0 reset mode. ( note 5-3 ) 1 1 1 full usb operation as described in section 6.0 . figure 5-5: ulpi start-up timing dir resetb stp t start refclk t1 t2 t0 supplies stable phy drives idle data[7:0] refclk valid phy tri-states phy tri-states phy drives high link drives low rxcmd idle idle
USB3370 ds00001915b-page 24 ? 2012 - 2015 microchip technology inc. 5.7 usb on-the-go (otg) the USB3370 provides support for the usb otg protocol. otg allows the USB3370 to be dynamically configured as a host or peripheral depending on the type of cable inserted into the micro-ab receptacle. when the micro-a plug of a cable is inserted into the micro-ab receptacle, the usb dev ice becomes the a-device. when a micro-b plug is inserted, the device becomes the b-device. the otg a-device behaves similar to a host while the b-device behaves similar to a peripheral. the differences are covered in the ?on-the-go supplement to the usb 2.0 specification?. in applications where only usb host or usb peripheral is required, the otg module is unused. 5.7.1 id resistor detection the id pin of the usb connector is monitored by the id pin of the USB3370 to detect th e attachment of different types of usb devices and cables. for device only appl ications that do not use the id signal the id pin should be connected to vdd33 . the block diagram of the id detection circuitry is shown in figure 5-6 and the related parameters are given in table 4-8 . 5.7.1.1 usb otg operation the USB3370 can detect id grounded and id floating to determine if an a or b cable has been inserted. the a plug will ground the id pin while the b plug will float the id pin. these are the only two valid st ates allowed in the otg protocol. to monitor the status of the id pin, the link activates the idpullup bit in the otg control register, waits 50ms and then reads the status of the idgnd bit in the usb interrupt status register. if an a cable has been inserted the idgnd bit will read 0. if a b cable is inserted, the id pin is floating and the idgnd bit will read 1. the USB3370 provides an integrated weak pull-up resistor on the id pin, r idw . this resistor is present to keep the id pin in a known state when the idpullup bit is disabled and the id pin is floated. in addition to keeping the id pin in a known state, it enables the USB3370 to generate an interr upt to inform the link when a cable with a resistor to ground has been attached to the id pin. the weak pull-up is small enough that the largest valid rid resistor pulls the id pin low and causes the idgnd comparator to go low. after the link has detected an id pin state change, the rid converter can be used to determine the resistor value as described in section 5.7.1.2 . figure 5-6: USB3370 id resistor detection circuitry idpullup idgnd v ref idgnd r id =100k r idw >1m idfloat id ~ ~ ~ ~ otg module vdd33 to usb con. ridvalue v ref idfloat idgnd rise or idgnd fall idfloatrise or idfloatfall rid adc idgnddrv en en
? 2012 - 2015 microchip technology inc. ds00001915b-page 25 USB3370 5.7.1.2 measuring id resistance to ground the link can use the integrated resist ance measurement capabilities of the USB3370 to determine the value of an id resistance to ground. the following table details the valid va lues of resistance to ground that the USB3370 can detect. the id resistance to ground can be read while the USB3370 is in synchronous mode. when a resistor to ground is attached to the id pin, the state of the idgnd comparator will change. after the link has detected id transition to ground, it can use the methods described in section 6.8 to operate the rid converter. 5.7.1.3 using idfloat comparator (not recommended). the id pin can be either grounded, floated, or connected to ground with a 102k ? external resistor. to detect the 102k resistor, set the idpullup bit in the otg control register, causing the USB3370 to apply the 100k internal pull-up con- nected between the id pin and vdd33. set the idfloatrise and idfloatfall bits in the carkit interrupt enable register to enable the idfloat comparator to generate an rxcmd to the link when the state of the idfloat changes. as described in figure 6-3 , the alt_int bit of the rxcmd will be set. the values of idgnd and idfloat are shown for the three types cables that can attach to the usb connector in ta b l e 5 - 3 . to save current when an a plug is inserted, the internal 102k ? pull-up resistor can be disabled by clearing the idpullup bit in the otg control register and the idfloatrise and idfloatfall bits in both the usb interrupt enable rising and usb interrupt enable falling registers. if the cable is removed the weak r idw will pull the id pin high. the idgnd value can be read using the ulpi usb interrupt status register, bit 4. in host mode, it can be set to generate an interrupt when idgnd changes by setting the appropriate bits in the usb interrupt enable rising and usb interrupt enable falling registers. the idfloat value can be read by reading the ulpi carkit interrupt status register bit 0. figure 5-7: valid values of id resistance to ground id resistance to ground rid value ground 000 75 ? +/-1% 001 102k ? +/-1% 010 200k ? +/-1% 011 floating 101 note: idpullup = 0 note: the ulpi specification details a method to detect a 102k ? resistance to ground using the idfloat compar- ator. this method can only detect 0ohms, 102k ? , and floating terminations of the id pin. due to this limita- tion it is recommended to use the rid converter as described in section 5.7.1.2 . table 5-3: idgnd and idfloat vs. id resistance to ground id resistance idgnd idfloat float 1 1 102k 1 0 gnd 0 0 note: the ulpi register bits idpullup , idfloatrise, and idfloatfall should be enabled. note: the idgnd switch has been provided to ground the id pin for future applications.
USB3370 ds00001915b-page 26 ? 2012 - 2015 microchip technology inc. 5.7.2 vbus monitoring and vbus pulsing the USB3370 includes all of the vbus comparators required for otg. the vbusvld, sessvld, and sessend compar- ators shown in figure 5-8 are fully integrated into the USB3370. these comparators are used to monitor changes in the vbus voltage, and the state of each comparator can be read from the usb interrupt status register. the vbusvld comparator is used by the link, when configured as an a device, to ensure that the vbus voltage on the cable is valid. the sessvld comparator is used by the link when configured as both an a or b device to indicate a ses- sion is requested or valid. finally the sessend comparator is used by the b-device to indicate a usb session has ended. also included in the vbus monitor and pulsing block are the resistors used for vbus pulsing in srp. the resistors used for vbus pulsing include a pull-down to ground and a pull-up to vdd33 . in some applications, voltages much greater than 5.5v ma y be present at the vbus pin of the usb connector. the USB3370 includes an over voltage protection circuit that protects the vbus pin of the USB3370 from excessive volt- ages as shown in figure 5-8 . 5.7.2.1 sessend comparator the sessend comparator is used during the session request protocol (srp). the comparat or is used by the b-device to detect when a usb session has ended and it is safe to start vbus pulsing to request a usb session from the a- device. when vbus goes below the threshold in table 4-7 , the usb session is considered to be ended, and sessend will transition from 0 to 1. the sessend comparator can be disabled by clearing this bit in both the usb interrupt enable rising and usb interrupt enable falling registers. when disabled, the sessend bit in the usb interrupt status register will read 0. the sessend comparator is only used when configured as an ot g device. if the USB3370 is used as a host or device only the sessend comparator should be di sabled, using the method described above. figure 5-8: USB3370 otg vbus block r vpd vbusvalid sessvalid sessend dischrgvbus 0.5v 1.4v 4.575v vbus ~ ~ ~ ~ vdd33 phy to usb con. sessend rise or sessend fall vbusvalid rise or vbusvalid fall rxcmd vbusvalid indicatorcomplement [useexternalvbusindicator, indicatorpassthru] [0, x] [1, 0] [1, 1] r vb r vpu chrgvbus vbus overvoltage protection r vbus en en extvbus
? 2012 - 2015 microchip technology inc. ds00001915b-page 27 USB3370 5.7.3 sessvld comparator the sessvld comparator is used when the phy is configured as both an a and b device. when configured as an a device, the sessvld is used to detect session request protocol (srp). when co nfigured as a b device, sessvld is used to detect the presence of vbus. the sessvld co mparator output can also be read from the usb interrupt status regis- ter. the sessvld comparator will also generate an rx cmd, as detailed in section 6.3.1 , anytime the comparator changes state. the sessvld interrupts can be di sabled by clearing this bit in both the usb interrupt enable rising and usb interrupt enable falling registers. when the interrupts are disabled, the sessvld comparator is still operational and will generate rx cmd?s. the sessvld comparator trip point is detailed in table 4-8 . 5.7.3.1 vbusvld comparator the vbusvld comparator is only used when the USB3370 is configured as a host that can supply less than 100ma vbus current. in the usb protocol, the a-device supplies t he vbus voltage and is responsible to ensure it remains within a specified voltage range. the vbus vld comparator can be disabled by clearing this bit in both the usb interrupt enable rising and usb interrupt enable falling registers. when disabled, bit 1 of the usb interrupt status register will return a 0. the vbusvld comparator threshold values are detailed in ta b l e 4 - 8 . if the USB3370 is used as a device only the vbusvalid co mparator should be disabled, using the method described above. the USB3370 includes the external vbusvld indicator logic as detailed in the ulpi specification. the external vbusvld indicator is tied to a logic one. the decoding of this logic is shown in ta b l e 5 - 4 below. by default this logic is disabled. note 5-4 a peripheral should not use vbusvld to begin operat ion. the peripheral should use sessvld to detect the presence of vbus on the usb connector. vbusvld should only be used for usb host and otg a-device applications. 5.7.3.2 vbus pulsing with pull -up and pull-down resistors in addition to the internal vbus comparators, the usb33 70 also includes the integrated vbus pull-up and pull-down resistors used for vbus pulsing during otg session request protocol. to discharge the vbus voltage so that a ses- sion request can begin, the USB3370 provides a pull-down resistor from vbus to gnd . this resistor is controlled by the dischargevbus bit 3 of the otg control register. the pull-up resistor is connected between vbus and vdd33. this resistor is used to pull vbus above 2.1 volts so that th e a-device knows that a usb session has been requested. the state of the pull-up resistor is controlled by the bit 4 chargevbus of the otg control register. the pull-up and pull-down resistor values are detailed in ta b l e 4 - 8 . the internal vbus pull-up and pull-down resistors are designed to include the r vbus external resistor in series. this external resistor is used by the vbus over voltage protection described below. note: the otg supplement specifies a voltage range for a-device session valid and b-device session valid comparator. the USB3370 phy combines the two comparators into one and uses the narrower threshold range. table 5-4: external vbus indicator logic typical application use external vbus indicator indicator pass thru indicator complement rxcmd vbus valid encoding source otg device 0 x x internal vbusvld comparator (default) 1 1 0 fixed 1 1 1 1 fixed 0 1 0 0 internal vbusvld comparator. 1 0 1 fixed 0 standard host 1 1 0 fixed 1 1 1 1 fixed 0 standard peripheral 0 x x internal vbusvld comparator. this information should not be used by the link. ( note 5-4 )
USB3370 ds00001915b-page 28 ? 2012 - 2015 microchip technology inc. 5.7.3.3 vbus input impedance the otg supplement requires an a-devi ce that supports session request protocol to have a vbus input impedance less than 100k ? and greater the 40k ? to ground. the USB3370 provides a 75k ? resistance to ground, r vb . the r vb resistor tolerance is detailed in ta b l e 4 - 8 . 5.7.3.4 vbus over voltage protection (ovp) the USB3370 provides an integrated over vo ltage protection circuit to protect the vbus pin from excessive voltages that may be present at the usb connec tor. the over voltage protection circuit works with an external resistor (r vbus ) by drawing current across the resist or to reduce the voltage at the vbus pin. when voltage at the vbus pin exceeds 5.5v, the over voltage protecti on block will sink current to ground until vbus is below 5.5v. the current drops the excess voltage across r vbus and protects the USB3370 vbus pin. the required r vbus value is dependent on the operating mode of the USB3370 as shown in table 5-5 . the over voltage protection circuit is designed to protec t the USB3370 from continuous voltages up to 30v on the r vbus resistor. the r vbus resistor must be sized to handle the power dissipated across the resistor. the resistor power can be found using the equation below: for example, protecting a peripheral or devic e only application to 15v would require a 20k ? r vbus resistor with a power rating of 0.05w. to protect an otg product to 15v would require a 1k ? r vbus resistor with a power rating of 0.1w. 5.7.4 driving external vbus the USB3370 monitors vbus as described in vbus monitoring and vbus pulsing . for otg and host applications, the system is required to source 5 volts on vbus. the USB3370 fully supports vbus power control using an external vbus switch. the USB3370 provides an open drain active low control signal, cpen_n , that is dedicated to controlling the vbus supply when configured as an a-device. cpen_n is driven by setting the drvvbus or drvvbusexternal bit of the otg control register. to be compatible with link designs that support both inter nal and external vbus supplies, the drvvbus and drvvbusexternal bits in the otg control register are nor?d together. this enables the li nk to set either bit to access the external vbus enable ( cpen_n ). this logic is shown in figure 5-9 . drvvbus and drvvbusexternal are set to 0 on power on reset (por) as shown in section 7.1.1.7 . table 5-5: required r vbus resistor value operating mode r vbus device only 20k ? 5% otg host capable of less than 100ma of current on vbus 1k ? 5% host or otg host capable of >100ma useexternalvbusindicator = 1 20k ? 5% p rvbus vprotect 5.0 ? () 2 r vbus ------------------------------------------- - = where: ? vprotect is the vbus protection required. ?r vbus is the resistor value, 1k ? or 20k ? . ?p rvbus is the required power rating of r vbus.
? 2012 - 2015 microchip technology inc. ds00001915b-page 29 USB3370 5.7.5 external vbus indicator the USB3370 has fully implemented the external vbus detecti on described in the ulpi 1.1 specification. the block diagram of the external vbus detection is shown in figure 5-8 and in ta b l e 5 - 4 . note 5-5 microchip does not recommend using the externalvbus signal qualified with the internal vbusvld comparator. note 5-6 a peripheral should not use vbusvld to begin operation. the peripheral should use sessvld because the internal vbusvld threshold can be above the v bus voltage required for usb peripheral operation. a host phy may use an active high or low fault by setting the indicatorcomplement bit [5] in the interface control reg- ister. also this implementation supports the indicatorpassthru bit [6] in the interface control register, which allows a choice of having the external vbus inpu t qualified (and?ed) with the external vbus comparator output. to use the external vbus input the useexternalvbusindicator bit [7] must be set in the otg control register. the default is not to use this input. the extvbus pin has a built in pull down resistor that is controlled by the useexternalvbusindicator bit [7] of the otg control register. when useexternalvbusindicator is set to 0 (default) the pull down resistor is activated to prevent the pin from floating when it is unused. when useexternalvbusindicator is set to 1 the pull down resistor is disconnected. figure 5-9: USB3370 drives control sig nal (cpen_n) to external vbus switch table 5-6: external vbus indicator logic typical application use external vbus indicator indicator pass thru indicator complement rxcmd vbus valid encoding source otg device 0 x x internal vbusvld comparator (default) 1 1 0 external active high vbusvld signal 1 1 1 external active low vbusvld signal 1 0 0 external active high power fault signal qualified with internal vbusvld comparator. ( note 5-5 ) 1 0 1 external active low power fault signal qualified with internal vbusvld comparator. ( note 5-5 ) standard host 1 1 0 external active high power fault signal 1 1 1 external active low power fault signal standard peripheral 0 x x internal vbusvld comparator. this should not be used by the link. ( note 5-6 ) vbus switch out en in 5v usb transceiver vbus usb connector dm dp vbus r vbus cpen_n link controller cpen_n logic drvvbusexternal drvvbus dm dp ulpi +5v vbus supply r pu
USB3370 ds00001915b-page 30 ? 2012 - 2015 microchip technology inc. 5.8 usb uart support the USB3370 provides support for the usb uart interface as detailed in the ulpi specification and the former cea- 936a specification. the USB3370 can be placed in uart mode using the method described in section 6.7 , and the regulator output will automatically switch to the value configured by the uart regoutput bits in the usb io & power management register. while in uart mode, the linestate signals cannot be monitored on the data[0] and data[1] pins. 5.9 usb charger detection support the following blocks allow t he USB3370 to detect when a ba ttery charger, charging ho st port, or a usb host is attached to the usb connector. the USB3370 can also be conf igured to appear as a charging host port, all according to the usb-if battery charging 1.1 sp ecification. the charger det ection circuitry should be disabled during usb oper- ation. the charger detection circuitry runs from the vdd33 supply and requires that the vdd33 supply to be present to run the charger detection circuitry. the vdd33 supply is present anytime the resetb pin is pulled high and vbat is pres- ent. the charger detection circuits are fully functional while in low power mode ( suspendm = 0). the status of the vdat- det can be relayed back to the link through the ulpi in terrupts in both synchronous mode and low power mode. figure 5-10: usb charger detection block diagram note: the italic names in the figure 5-10 correspond to bits in the ulpi register set. v dat_ref dp ~ ~ ~ ~ vdd33 phy to usb con. r cd chargerpullupendp en dm to usb con. r cd chargerpullupendm idatsinken hostchrgen vdatdet vdatsrcen i dat_sink en v dat_src contactdetecten i dp_src en dppulldown dmpulldown r pd r pd
? 2012 - 2015 microchip technology inc. ds00001915b-page 31 USB3370 5.9.1 active analog charger detect ion (usb-if battery charging 1.1) the USB3370 includes the active analog charger detection s pecified in the usb-if battery charging specification. the additional analog circuitry will allow the USB3370 to: 1. detect a dedicated charging port (dcp) with the dp and dm pi ns shorted together. 2. detect a standard downstream port (sdp ) which has no battery charging circuitry. 3. detect a charging downstream port (cdp) which active ly supplies voltage to the dm pin when connected to a usb-if bc 1.1 compatible device. 4. behave as a charging downstream port by enabling the voltage source on the dm pin. the charger detection circuitry is shown in figure 5-10 . the vdatdet output is qualified with the linestate[1:0] value. if the linestate is not equal to 00 the vdatdet signal will not assert. the proper detection process flows through different modes of detection and uses the li nestate and vdatdet signals values to determine the connection. ta b l e 5 - 7 describes the bit values that need to be set to enter each mode. 5.9.1.1 example charger detection flow - dedicated charging port the usb-if battery charging 1.1 specific ation describes in detail the flow for ea ch charger type, but below is an exam- ple of the flow used to detect a dedicated charger (dcp). 1. device detects vbus voltage is pr esent from rxcmd, (sess_vld is 1) 2. device enters the device connect detect mode. - if the linestate still equals 10 after a specified timeout, the charger is an unknown charger and there will be no attempted usb enumeration. - if the linestate equals 00 or 11, the device will go to the next mode: 3. device enters device charger detection mode. - if the vdatdet bit is 0 then the host is a standard do wnstream port (sdp) and the device will draw the stan- dard 500ma of current and enter the device usb operation mode. - if the vdatdet bit is 1 then the host is a charger that can supply at least 1.5a of current, the device will go to the next mode. 4. device enters device enhanced charger detection mode. - if the vdatdet bit is 0 then the device is connected to a charging downstream port (cdp) and the device will enter the device usb operation mode. - if the vdatdet bit is 1 then the device is connected to a dedicated charging port (dcp) and the device will not try to enumerate. 5. the charger detection is complete. table 5-7: usb charger setting vs. modes charger detection modes vdatsrcen idatsinken contactdeten hostchrgen dppulldown dmpulldown device connect detect (the connect detect setting in ta b l e 5 - 1 must be followed) 001001 device charger detection 110000 device enhanced charger detection 1 1 0100 device usb operation 000000 charging host port, no charging device attached and se0 ( vdatdet = 0) 010111 charging host port, charging device attached ( vdatde t = 1)110111 charging host port usb operation 000111
USB3370 ds00001915b-page 32 ? 2012 - 2015 microchip technology inc. 5.9.2 resistive charger detection to support the detection and identification of different ty pes of usb chargers the usb3 370 provides integrated pull-up resistors, r cd , on both dp and dm . these pull-up resistors along with the single ended receivers can be used to deter- mine the type of usb charger attached. reference info rmation on implementing charger detection is provided in section 8.2 . note: the resistive charger detection has been superseded by the active analog charger detection (usb-if battery charging 1.1) detailed above. it is recomm ended that new designs use the active analog charger detection (usb-if battery charging 1.1) . table 5-8: usb weak pull-up enable resetb dp pullup enab le dm pullup enable 00 0 1 chargerpullupenabledp chargerpullupenabledm note: chargerpullupenabledp and chargerpullupenabledm are enabled in the usb io & power management register.
? 2012 - 2015 microchip technology inc. ds00001915b-page 33 USB3370 6.0 ulpi operation 6.1 ulpi introduction the USB3370 uses the industry standard ulpi digital inte rface for communication between the transceiver and link (device controller). the ulpi interface is designed to reduce the number of pi ns required to connect a discrete usb transceiver to an asic or digital controller. for example, a full utmi+ level 3 otg interface requires 54 signals while a ulpi interface requires only 12 signals. the ulpi interface is documented completely in the ?utmi+ low pin interface (ulpi) specification revision 1.1?. the following sections describe the operating modes of the usb3 370 digital interface.enhanced single supply hi-speed usb ulpi transceiver figure 6-1 illustrates the block diagram of the ulpi digital functi ons. it should be noted that this USB3370 does not use a ?ulpi wrapper? around a utmi+ phy core as the ulpi specification implies. the advantage of a ?wrapper-less? architecture is that the USB3370 has a lower usb latency than a design which must first register signals into the phy?s wrapper before the transf er to the transceiver core. a low latency phy allows a wrap- per around a utmi link to be used and still make the required usb turn-around timing required by the usb 2.0 speci- fication. figure 6-1: ulpi di gital block diagram note: the ulpi interface is a wrapperless design. por ulpi register array interrupt control 6pinserial mode xcvrselect[1:0] termselect opmode[1:0] reset suspendm 3pinserial mode clocksuspendm autoresume dischrgvbus chrgvbus idgnddrv dppulldown dmpulldown swapdp/dm carkitmode regoutput[1:0] chargerpullupendp chargerpullupendm txden rxden indicator complement indicator pass thru useexternal vbus indicator idpullup linestates[1:0] hostdisconnect interface protect disable vbusvalid sessionvalid sessionend idgnd idfloat ridcon...start ridvalue[2:0] ridcon...done data[7:0] high speed tx full speed tx low speed tx high speed data recovery full / low speed data recovery ulpi protocol block hs tx data fs/ls tx data hs rx data fs/ls data dir nxt stp tx data rx data usb transmit and receive logic ulpi register access resetb ulpi interupt rid state machi ne to rx analog to tx analog transceiver control to otg analog to usb analog
USB3370 ds00001915b-page 34 ? 2012 - 2015 microchip technology inc. rxenddelay maximum allowed by the ut mi+/ulpi for 8-bit data is 63 hi-spe ed clocks. USB3370 uses a low latency hi-speed receiver path to lo wer the rxenddelay to 43 hi-s peed clocks. this low laten cy design gives the link more cycles to make decisions and reduces the link complexity. this is the result of the ?wrapper less? architecture of the USB3370. this low rxenddelay should allow legacy utmi li nks to use a ?wrapper? to convert the utmi+ interface to a ulpi interface. in figure 6-1 , a single ulpi protocol block decodes the ulpi 8-bit bi-directional bus when the link addresses the phy. the link must use the dir output to determine direction of the ulpi data bus. the USB3370 is the ?bus arbitrator?. the ulpi protocol block will route data/commands to the transmitter or the ulpi register array. 6.1.1 ulpi interface signals the utmi+ low pin interface (ulpi) uses a 12-pin interface to connect a usb transceiver to an external link. the reduction of external pins, relative to utmi+, is accomplishe d implementing the relatively st atic configuration pins (i.e. xcvrselect[1:0], termselect, opmode[1:0], and dppulldo wn dmpulldown) as an internal register array. an 8-bit bi-directional data bus clocked at 60mhz allows the li nk to access this internal register array and transfer usb packets to and from the phy. the remaining 3 pins function to control the data flow and arbitrate the data bus. direction of the 8-bit data bus is controlled by the dir output from the phy. another output, nxt , is used to control data flow into and out of the device. finally, stp , which is in input to the phy, terminates transfers and is used to start up and resume from low power mode. the ulpi interface signals are described below in table 6-1 . USB3370 implements a single data rate (sdr) ulpi in terface with all data transfers happening on the rising edge of the 60mhz ulpi clock while operating in synchronous mode. the direction of the data bus is determined by the state of dir . when dir is high, the phy is driving data[7:0] . when dir is low, the link is driving data[7:0] . each time dir changes, a ?turn-around? cycle occurs where neither the link nor phy drive the data bus for one clock cycle. during the ?turn-ar ound?cycle, the state of data[7:0] is unknown and the phy will not read the data bus. because usb uses a bit-stuffing encodi ng, some means of allowing the phy to throttle the usb transmit data is needed. the ulpi signal nxt is used to request the next byte to be placed on the data bus by the link. the ulpi interface supports the two basic modes of operation: synchronous mode and asynchronous mode. asynchro- nous mode includes low power mode, the serial modes, an d carkit mode. in synchronous mode, all signals change synchronously with the 60mhz ulpi clock. in asynchronous modes the clock is off and the ulpi bus is redefined to bring out the signals required for that particular mode of operations. the description of synchronous mode is described in the following sections while the descriptions of the asynchronous modes are described in section 6.5 , section 6.6 , and section 6.7 . table 6-1: ulpi interface signals signal direction description clk i/o 60mhz ulpi clock. all ulpi signals are driven synchronous to the rising edge of this clock. this clock can be either driven by the phy or the link as described in section 5.5.1 data[7:0] i/o 8-bit bi-directional data bus. bus ownersh ip is determined by dir. the link and phy initiate data transfers by driving a non-zer o pattern onto the data bus. ulpi defines interface timing for a single-edge data transfers with respect to rising edge of the ulpi clock. dir out controls the direction of the data bus. when the phy has data to transfer to the link, it drives dir high to take ownership of the bus. when the phy has no data to transfer it drives dir low and monitors the bus for commands from the link. the phy will pull dir high whenever the interface can not accept data from the link, such as during pll start-up. stp in the link asserts stp for one clock cycle to stop the data stream currently on the bus. if the link is sending data to the phy, stp indicates the last byte of data was on the bus in the previous cycle. nxt out the phy asserts nxt to throttle the data. when the link is sending data to the phy, nxt indicates when the current byte has been accepted by the phy. the link places the next byte on the data bus in th e following clock cycle.
? 2012 - 2015 microchip technology inc. ds00001915b-page 35 USB3370 6.1.2 ulpi interface timing in synchronous mode the control and data timing relationships are given in figure 6-2 and ta b l e 4 - 3 . all timing is relative to the rising clock edge of the 60mhz ulpi clock. 6.2 ulpi register access the following section details the steps required to access registers through the ulpi interface. at any time dir is low the link may access the ulpi registers set using the trans mit command byte. the ulpi registers retain their contents when the phy is in low power mode, full speed/low speed serial mode, or carkit mode. 6.2.1 transmit command byte (tx cmd) a command from the link begins a ulpi transfer from the li nk to the USB3370. before reading a ulpi register, the link must wait until dir is low, and then send a transmit command byte (tx cmd) byte. the tx cmd byte informs the USB3370 of the type of data being sent. the tx cmd is followed by a data transfer to or from the USB3370. table 6-2 gives the tx command byte (tx cmd) encoding for the usb3 370. the upper two bits of the tx cmd instruct the phy as to what type of packet the link is transmitting. figure 6-2: ulpi single data rate timing diagram in synchronous mode table 6-2: ulpi tx cmd byte encoding command name cmd bits[7:6] cmd bits[5:0] command description idle 00b 000000b ulpi idle transmit 01b 000000b usb transmit packet with no packet identifier (nopid) 00xxxxb usb transmit packet identifier (pid) where data[3:0] is equal to the 4-bit pid. p 3 p 2 p 1 p 0 where p 3 is the msb. register write 10b xxxxxxb immediate register write command where: data[5:0] = 6-bit register address 101111b extended register write command where the 8-bit register address is available on the next cycle. 60mhz ulpi - clk control in - stp data in - data[7:0] control out - dir, nxt data out - data[7:0] t sc t sd t hc t hd t dc t dc t dd
USB3370 ds00001915b-page 36 ? 2012 - 2015 microchip technology inc. 6.2.2 ulpi register write a ulpi register write operation is given in figure 6-3 . the tx command with a register write data[7:6] = 10b is driven by the link at t0. the register address is encoded into data[5:0] of the tx cmd byte. to write a register, the link will wait until dir is low, and at t0, drive the tx cmd on the data bus. at t2 the phy will drive nxt high. on the next rising clock edge, t3, the link will write the register data. at t4, the phy will accept the register data and drive nxt low. the link will drive an idle on the bus and drive stp high to signal the end of the data packet. finally, at t5, the phy will latch the dat a into the register and the link will pull stp low. nxt is used to throttle when the link dr ives the register data on the bus. dir is low throughout this transaction since the phy is receiving data from the link. stp is used to end the transaction and dat a is registered after the de-assertion of stp . after the write operation completes, the link must drive a ulpi idle (00h) on the data bus. if the databus is not driven to idle the USB3370 may decode the non-zero bus value as an rx command. a ulpi extended register write operation is shown in figure 6-4 . to write an extended register, the link will wait until dir is low, and at t0, drive the tx cmd on the data bus. at t2 the phy will drive nxt high. on the next clock t3 the link will drive the extended address. on the next rising clock edge, t4, the link will write the register data. at t5, the phy will accept the register data and drive nxt low. the link will drive an idle on the bus and drive stp high to signal the end of the data packet. at t5, the phy will latch the data into the register. finally, at t6, the link will drive stp low. register read 11b xxxxxxb immediate register read command where: data[5:0] = 6-bit register address 101111b extended register read command where the 8-bit register address is available on the next cycle. figure 6-3: ulpi register write in synchronous mode table 6-2: ulpi tx cmd byte encoding (continued) command name cmd bits[7:6] cmd bits[5:0] command description dir clk data[7:0] stp nxt txd cmd (reg write) idle reg data[n] idle ulpi register reg data [n-1] reg data [n] t0 t1 t2 t3 t5 t4 t6
? 2012 - 2015 microchip technology inc. ds00001915b-page 37 USB3370 6.2.3 ulpi register read a ulpi register read operation is given in figure 6-5 . the link drives a tx cmd byte with data[7:6] = 11h for a register read. data[5:0] of the ulpi tx command bye contain the register address. at t0, the link will place the tx cmd on the data bus. at t2, the phy will bring nxt high, signaling the link it is ready to accept the data transfer. at t3, the phy reads the tx cmd, determines it is a register read, and asserts dir to gain control of the bus. the phy will also de-assert nxt . at t4, the bus ownership has transferred back to the phy and the figure 6-4: ulpi extended regist er write in synchronous mode figure 6-5: ulpi register read in synchronous mode dir clk data[7:0] stp nxt txd cmd (extended reg write) idle reg data[n] idle ulpi register reg data [n-1] reg data [n] t0 t1 t2 t3 t5 t4 t6 extended address t7 dir clk data[7:0] stp nxt txd cmd reg read idle t0 reg data turn around turn around t1 t2 t3 t4 t5 t6 idle
USB3370 ds00001915b-page 38 ? 2012 - 2015 microchip technology inc. phy drives the requested register onto the data bus. at t5, the link will read the data bus and the phy will drop dir low returning control of the bus back to the link. after the turn around cycle, the link must drive a ulpi idle command at t6. a ulpi extended register r ead operation is shown in figure 6-6 .to read an extended register, the link writes the tx cmd with the address set to 2fh. at t2, the phy will assert nxt , signaling the link it is ready to accept the extended address. at t3, the link places the ex tended register address on the bus. at t4, the phy reads the extended address, and asserts dir to gain control of the bus. the phy will also de-assert nxt . at t5, the bus ownership has transferred back to the phy and the phy drives the requested register on to the data bus. at t6, the link will read the data bus and the phy will de-assert dir returning control of the bus back to the link. after the turn around cycle, the link must drive a ulpi idle command at t6. 6.3 USB3370 receiver the following section describes how the u sb3370 uses the ulpi interface to rece ive usb signaling and transfer status information to the link. this information is communicated to the link using rx commands to relay bus status and received usb packets. 6.3.1 ulpi receive command (rx cmd) the ulpi link needs information which was provided by t he following pins in a utmi implementation: linestate[1:0], rxactive, rxvalid, rxerror, and vbusvalid . when implementing the otg functions, the vbus and id pin states must also be transferred to the link. ulpi defines a receive comm and byte (rxcmd) that contains this information. an rxcmd can be sent a any time the bus is idle. the rxcmd is initiated when the USB3370 asserts dir to take con- trol of the bus. the timing of rxcm d is shown in the figure below. the USB3370 can send single or back to back rxcmd?s as required. the encoding of the rxcmd byte is given in the table 6-3 . figure 6-6: ulpi extended regist er read in synchronous mode dir clk data[7:0] stp nxt txd cmd extended reg read idle t0 reg data turn around turn around t1 t2 t3 t4 t5 t6 idle extended address t7
? 2012 - 2015 microchip technology inc. ds00001915b-page 39 USB3370 transfer of the rxcmd byte occurs in synchronous mode when the phy has control of the bus. the ulpi protocol block shown in figure 6-1 determines when to send an rxcmd. a rxcmd will occur: ? when a linestate change occurs. ? when vbus or id comparators change state. ? during a usb receive when nxt is low. ? after the USB3370 deasserts dir and stp is low during start-up ? after the USB3370 exits low power mode, serial modes, or carkit mode after detecting that the link has de- asserted stp , and dir is low. when a usb receive is occurring, rxcmd?s are sent whenever nxt = 0 and dir = 1. during a usb transmit, the rxcmd?s are returned to the link after stp is asserted. if an rxcmd event occurs during a hi-speed usb transmit, the rxcmd is blocked until stp de-asserts at the end of the transmit. the rxcmd contains the status that is current at the time the rxcmd is sent. figure 6-7: ulpi rxcmd timing table 6-3: ulpi rx cmd encoding data [7:0] name description and value [1:0] linestate utmi linestate signals. see section 6.3.1.1 [3:2] encoded vbus state encoded vbus voltage states value vbus voltage sessend sessvld vbusvld 2 00 v vbus < v sess_end 10 0 01 v sess_end < v vbus < v sess_vld 00 0 10 v sess_vld < v vbus < v vbus_vld x1 0 11 v vbus_vld < v vbus xx 1 [5:4] rx event encoding encoded utmi event signals value rxactive rxerror hostdisconnect 00 0 0 0 01 1 0 0 11 1 1 0 10 x x 1 dir clk data[7:0] stp nxt rxcmd idle idle t0 t1 t2 t3 t5 t4 t6 turn around turn around rxcmd idle turn around turn around rxcmd t7 t8
USB3370 ds00001915b-page 40 ? 2012 - 2015 microchip technology inc. note 1: an ?x? is a do not care and can be either a logic 0 or 1. 2: the value of vbusvalid is defined in table 5-4 . 6.3.1.1 definition of linestate the linestate information is used to relay information back to the link on the current status of the usb data lines, dp and dm . the definition of linestate changes as the usb33 70 transitions between ls/f s mode, hs mode, and hs chirp. 6.3.1.1.1 ls/fs linestate definitions in ls and fs operating modes the linestate is defined by the outputs of the ls/fs single ended receivers (se rx). the logic thresholds for single ended receivers, v ilse and v ilse are shown in ta b l e 4 - 5 . low speed uses the same linestate decoding threshold as full speed. low speed re-defines the idle state as an inver- sion of the full speed idle to account for the inversion wh ich occurs in the hub repeater path. linestates are decoded exactly as in table 6-4 with the idle as a k state. 6.3.1.1.2 hs linestate definition in hs mode the data transmission is too fast for linestate to be transmitted with each transition in the data packet. in hs operation the linestate is redefined to indicate activity on the usb interface. the linestate will signal the assertion and de-assertion of squelch in hs mode. [6] state of id pin set to the logic state of the id pin. a logic low indicates an a device. a logic high indicates a b device. [7] alt_int asserted when a non-usb interrupt o ccurs. this bit is set when an unmasked event occurs on any bit in the carkit interrupt latch register. the link must read the carkit interrupt latch register to determine th e source of the interrupt. section 6.8 describes how an interrupt can be generated when the ridconversiondone bit is set. table 6-4: usb linestate decoding in fs and ls mode linestate[1:0] dp se rx dm se rx state 00 se0 0 0 usb reset 01 j (fs idle) 1 0 j state 10 k (ls idle) 0 1 k state 11 se1 1 1 se1 table 6-5: usb linestate decoding in hs mode linestate[1:0] dp se rx dm se rx state 00 se0 0 0 hs squelch asserted 01 j 1 0 hs squelch de-asserted 10 k 0 1 invalid state 11 se1 1 1 invalid state table 6-3: ulpi rx cmd encoding (continued) data [7:0] name description and value
? 2012 - 2015 microchip technology inc. ds00001915b-page 41 USB3370 6.3.1.1.3 hs chirp linestate definition there is also a third use of linestate in hs chirp where when the host and peripheral negotiate the from fs mode to hs mode. while the transitions from k to j or se0 are communicated to the link through the linestate information. 6.3.2 usb receiver the USB3370 ulpi receiver fully supports hs, fs, and ls transmit operations. in all three modes the receiver detects the start of packet and synchronizes to the incoming data packet . in the ulpi protocol, a received packet has the priority and will immediately follow register reads and rxcmd transfers. figure 6-8 shows a basic usb pa cket received by the USB3370 over the ulpi interface. in figure 6-8 the phy asserts dir to take control of the data bus from the link. the assertion of dir and nxt in the same cycle contains additio nal information that rxacti ve has been asserted. when nxt is de-asserted and dir is asserted, the rxcmd data is transferred to the link. after the last byte of the usb receive packet is transferred to the phy, the linestate will return to idle. the ulpi full speed receiver operates ac cording to the utmi / ulpi specific ation. in the full speed case, the nxt signal will assert only when the data bus has a valid received data byte. when nxt is low with dir high, the rxcmd is driven on the data bus. in full speed, the USB3370 will not issue a rxactive de-a ssertion in the rxcmd until the dp/dm linestate transitions to idle. this prevents the link from violating the two full speed bit times minimum turn around time. table 6-6: usb linestate decoding in hs chirp mode linestate[1:0] dp se rx dm se rx state 00 se0 0 0 hs squelch asserted 01 j 1 0 hs squelch de-asserted & hs differential receiver = 1 10 k 0 1 hs squelch de-asserted & hs differential receiver = 0 11 se1 1 1 invalid state figure 6-8: ulpi rece ive in synchronous mode dir clk data[7:0] stp nxt rxd cmd idle turn around pid d1 rxd cmd d2 turn around
USB3370 ds00001915b-page 42 ? 2012 - 2015 microchip technology inc. 6.3.2.1 disconnect detection a hi-speed host must detect a disconnect by sampling the transmitter outputs during the long eop transmitted during a sof packet. the USB3370 only looks for a hi-speed disconnect during the long eop where the period is long enough for the disconnect reflection to return to the host phy. when a hi-speed disconnect occurs, the USB3370 will return a rxcmd and set the host disconnect bit in the usb interrupt status register. when in fs or ls modes, the link is expected to handle all disconnect detection. 6.3.2.2 link power management (lpm) token receive the USB3370 is fully capable of receiving the extended pi d in the lpm token. when the lpm 0000b pid is received, this information is passed to the link as a normal receive packet. if the link chooses to enter lpm suspend, the proce- dure detailed in section 6.5.3 can be followed. 6.4 USB3370 transmitter the USB3370 ulpi transmitter fully suppo rts hs, fs, and ls transmit operations. figure 6-1 shows the hi-speed, full speed, and low speed transmitter block controlled by ulpi pr otocol block. encoding of the usb packet follows the bit- stuffing and nrzi outlined in the usb 2.0 specification. many of these functions are reused between the hs and fs/ls transmitters. when using the USB3370, ta b l e 5 - 1 should always be used as a guideline on how to configure for various modes of operation. the tran smitter decodes the inputs of xcvrselect[1:0] , termselect , opmode[1:0] , dppulldown, and dmpulldown to determine what operation is expected. users must strictly adhere to the m odes of operation given in table 5-1 . several important functions for a device and host are designed into the transmitter blocks. the USB3370 transmitter will transmit a 32-bit long hi-speed sync before every hi-speed packet. in full and low speed modes a 8-bit sync is transmitted. when the device or host needs to chirp for hi-speed port negotiation, the opmode = 10 setting will turn off the bit-stuffing and nrzi encoding in the transmitter. at the end of a chirp, the USB3370 opmode register bits should be changed only after the rxcmd linestate encoding indicates that the tran smitter has completed transmitting. should the opmode be switched to normal bit-stuffing and nrzi encoding before th e transmit pipeline is empty, the remaining data in the pipe- line may be transmitted in an bit-stuff encoding format. please refer to the ulpi specification for a detailed discussion of usb reset and hs chirp. 6.4.1 USB3370 host features the USB3370 can also support usb host operation and includes the following features that are required for host oper- ation. 6.4.1.1 hi-speed long eop when operating as a hi-speed host, the USB3370 will automatically generate a 40 bit long end of packet (eop) after a sof pid (a5h). the USB3370 determines wh en to send the 40-bit long eop by de coding the ulpi tx cmd bits [3:0] for the sof. the 40-bit long eo p is only transmitted when the dppulldown and dmpulldown bits in the otg control register are asserted. the hi-sp eed 40-bit long eop is used to detect a disconnect in mode. in device mode, the USB3370 will not send a long eop after a sof pid. 6.4.1.2 low speed keep-alive low speed keep alive is supported by the USB3370. when in low speed mode, the USB3370 will send out two low speed bit times of se0 when a sof pid is received. 6.4.1.3 utmi+ level 3 pre-amble is supported for utmi + level 3 compatibility. when xcvrselect is set to (11b) in host mode, ( dppulldown and dmpulldown both asserted) the USB3370 will pre-pend a full speed pre-amble before the low speed packet. full speed rise and fall times are used in this mode. the pre-amble consists of the following: full speed sync, the encoded pre-pid (c3h) and then full speed idle (dp=1 and dm = 0) . a low speed packet follows with a sync, data and a ls eop. the USB3370 will only support utmi+ level 3 as a host. th e USB3370 does not support utmi+ level 3 as a peripheral. a utmi+ level 3 peripheral is an upstream hub port. the USB3370 will not decode a pre-amble packet intended for a ls device when the USB3370 is configured as the upstream port of a fs hub, xcvrselect = 11b, dppulldown = 0b, dmpulldown =0b.
? 2012 - 2015 microchip technology inc. ds00001915b-page 43 USB3370 6.4.1.4 host resume k resume k generation is supported by the USB3370. at th e end of a usb suspend the phy will drive a k back to the downstream device. when the USB3370 exits from low po wer mode, when operating as a host, it will automatically transmit a resume k on dp/dm. the transmitters will end the k with se0 for two low speed bit times. if the USB3370 was operating in hi-speed mode before the suspend, the host must change to hi-speed mode before the se0 ends. se0 is two low speed bit times which is about 1.2 us. for mo re details please see sections 7.1.77 and 7. 9 of the usb specification. in device mode, the resume k will not append an se0, but release the bus to the correct idle state, depending upon the operational mode as shown in ta b l e 5 - 1 . the ulpi specification includes a detailed discussion of th e resume sequence and the orde r of operations required. to support host start-up of less than 1ms the USB3370 implements the ulpi autoresume bit in the interface control reg- ister. the default autoresume state is 0 and this bit should be enabled for host applications. 6.4.1.5 no sync and eop generation ( opmode = 11) utmi+ defines o pmode = 11 where no sync and eop generation occurs in hi-speed operation. this is an option to the ulpi specification and not implemented in the USB3370. 6.4.2 typical usb transmit with ulpi figure 6-9 shows a typical usb transmit sequence. a transmit sequence starts by the link sending a tx cmd where data[7:6] = 01b, data[5:4] = 00b, and data[3:0] = pid. the tx cmd with the pid is followed by transmit data. during transmit the phy will use nxt to control the rate of data flow into the phy. if the USB3370 pipeline is full or bit- stuffing causes the data pipeline to overfill nxt is de-asserted and the link will hold the value on data until nxt is asserted. the usb transmit ends when the link asserts stp while nxt is asserted. after the USB3370 completes transmitting, the dp and dm lines return to idle and a rxcmd is returned to the link so the inter-packet timers may be updated by linestate. while operating in full speed or low speed, an end-of-packe t (eop) is defined as se0 for approximately two bit times, followed by j for one bit time. the transceiver drives a j stat e for one bit time following the se0 to complete the eop. the link must wait for one bit time following line state indi cation of the se0 to j transition to allow the transceiver to complete the one bit time j state. all bit ti mes are relative to the speed of transmission. in the case of full speed or low speed, after stp is asserted each fs/ls bit transition will generate a rxcmd since the bit times are relatively slow. figure 6-9: ulpi transmit in synchronous mode note: the link cannot assert stp with nxt de-asserted since the USB3370 is expecting to fetch another byte from the link. data[7:0] dp/dm dir clk stp nxt txd cmd (usb tx) idle d0 d2 d3 idle se0 !squelch se0 turn around turn around rxd cmd d1
USB3370 ds00001915b-page 44 ? 2012 - 2015 microchip technology inc. 6.4.2.1 link power management token transmit a host link can send a lpm command using the USB3370. when sending the lpm token the normal transmit method is not used. sending a lpm token requires the USB3370 to se nd a 0000b or ?f0? pid. when the ulpi specification was defined the ?f0? pid was not defined. the ulpi specification used the ?reserved? ?f0? pid to signal chirp and resume signaling while using opmode 10b. while in opmode 00b the USB3370 is able to gener ate the ?f0? pid as shown below. to send the ?f0? pid, the link will be required to use the tx cmd with nopid to initiate the transmit and then follow up the tx cmd with the ?f0? pid. the data by tes follow as in a normal transmit, in opmode 00b. the key difference is in that the link will have to send the pid the same as it would send a data packet. the USB3370 is able to recognize the lpm transmit and correctly send the pid information. 6.5 low power mode low power mode is a power down state to save current w hen the usb session is suspended. the link controls when the phy is placed into or out of low power mode. in low power mode all of the circuits are powered down except the interface pins, full speed receiver, vbus comparators, and idgnd comparator. the vbus and id comparators can optionally be powered down to save current as shown in section 6.5.5 . before entering low power mode, the USB3370 must be confi gured to set the desired state of the usb transceiver. the xcvrselect[1:0] , termselect and opmode[1:0] bits in the function control register, and the dppulldown and dmpull- down bits in the otg control register control the co nfiguration as shown in ta b l e 5 - 1 . the dp and dm pins are config- ured to a high impedance state by configuring opmode[1:0] = 01 as shown in the programming example in ta b l e 6 - 8 . pull-down resistors with a value of approximately 2m ? are present on the dp and dm pins to avoid false linestate indi- cations that could result if the pins were allowed to float. 6.5.1 entering low power/suspend mode to enter low power mode, the li nk will write a 0 or clear the suspendm bit in the function control register. after this write is complete, the phy will assert dir high and after a minimum of five rising edges of clkout , drive the clock low. after the clock is stopped, the phy will enter a low power state to conserve current. placing the phy in suspend mode is not related to usb suspend. to clarify this point, usb suspend is initiated when a usb host stops data transmissions and enters full-speed mode with 15k ? pull-down resistors on dp and dm . the suspended device goes to full-speed mode with a pull-up on dp . both the host and device remain in this state until one of them drives dm high (this is called a resume). figure 6-10: lpm token transmit data[7:0] dp/dm dir clk stp nxt txd cmd (40h tx nopid ) idle pid (f0h) d1 idle se0 !squelch se0 turn around rxd cmd d0 turn around idle
? 2012 - 2015 microchip technology inc. ds00001915b-page 45 USB3370 while in low power mode, the data interface is redefined so that the link can monitor linestate and the vbus voltage. in low power mode data[3:0] are redefined as shown in ta b l e 6 - 7 . linestate[1:0] is the combinational output of the single-ended receivers. the ?int? or interrupt signal indi cates an unmasked interrupt has occurred. when an unmasked interrupt or linestate change has occurred, the link is notified and can determine if it should wake-up the phy. note 6-1 linestate: these signals reflect the current state of the full-speed single ended receivers. linestate[0] directly reflects the current state of dp . linestate[1] directly reflects the current state of dm . when dp = dm =0 this is called "single ended zero" (se0). when dp = dm =1, this is called "single ended one" (se1). an unmasked interrupt can be caused by the following comp arators changing state: vbusvld, sessvld, sessend, and idgnd. if any of these signals cha nge state during low power mode and the bits are enabled in either the usb interrupt enable rising or usb interrupt enable falling registers, data[3] will assert. during low power mode, the vbusvld and sessend comparators can have their interrupts masked to lower the suspend current as described in section 6.5.5 . while in low power mode, the data bus is driven asynch ronously because all of the phy clocks are stopped during low power mode. figure 6-11: entering low power mode from synchronous mode table 6-7: interface signal mapping during low power mode signal maps to direction description linestate[0] data[0] out combinatorial linestate[0] driven di rectly by the full-speed single ended receiver. note 6-1 linestate[1] data[1] out combinatorial linestate[1] driven di rectly by the full-speed single ended receiver. note 6-1 reserved data[2 ] out driven low int data[3] out active high interrupt indication. must be asserted whenever any unmasked interrupt occurs. reserved data[7:4] out driven low dir clk data[7:0] stp nxt txd cmd (reg write) idle reg data[n] idle t0 t1 t2 t3 t5 t4 t6 t10 turn around low power mode suspendm (ulpi register bit) ...
USB3370 ds00001915b-page 46 ? 2012 - 2015 microchip technology inc. 6.5.2 exiting low power mode to exit low power mode, the link will assert stp . upon the assertion of stp , the USB3370 will begin its start-up pro- cedure. after the phy start-up is complete, the phy will start the clock on clkout and de-assert dir . after dir has been de-asserted, the link can de-assert stp when ready and start operating in synchronous mode. the phy will auto- matically set the suspendm bit to a 1 in the function control register. the value for t start is given in ta b l e 4 - 2 . should the link de-assert stp before dir is de-asserted, the USB3370 will detect this as a false resume request and return to low power mode. this is detailed in section 3.9. 4 of the utmi+ low pin interf ace (ulpi) specification rev. 1.1. 6.5.3 link power management (lpm) when the USB3370 is operating with a link capable of link power management, the link will place the USB3370 in and out of suspend rapidly to conserve power. the USB3370 provides a fast suspend recovery that allows the USB3370 to meet the suspend recovery time detailed in the li nk power management ecn to the usb 2.0 specification. when the link places the USB3370 into suspend during link power management, the lpm enable bit of the hs com- pensation register must be set to 1. this allows the USB3370 to start-up in the time specified in table 4-2 . 6.5.4 interface protection ulpi protocol assumes that both the link and phy will keep the ulpi data bus driven by either the link when dir is low or the phy when dir is high. the only exception is when dir has changed state and a turn around cycle occurs for 1 clock period. in the design of a usb system, there ca n be cases where the link may not be driving the ulpi bus to a known state while dir is low. two examples where this can happen is because of a slow link start-up or a hardware reset. 6.5.4.1 start up protection upon start-up, when the phy de-asserts dir , the link must be ready to receive commands and drive idle on the data bus. if the link is not ready to receive commands or drive idle, it must assert stp before dir is de-asserted. the link can then de-assert stp when it has completed its start-up. if the link doesn?t assert stp before it can receive com- mands, the phy may interpret the data bus state as a tx cmd and transmit invalid data onto the usb bus, or make invalid register writes. figure 6-12: exiting low power mode dir clk data[7:0] stp turn around low power mode data bus ignored (slow link) idle (fast link) idle t0 t1 t2 t3 t5 t4 slow link drives bus idle and stp low fast link drives bus idle and stp low ... note: not to scale t start
? 2012 - 2015 microchip technology inc. ds00001915b-page 47 USB3370 when the USB3370 sends a rxcmd the link is required to driv e the data bus back to idle at the end of the turn around cycle. if the link does not drive the databus to idle the USB3370 may take the information on the data bus as a txcmd and transmit data on dp and dm until the link asserts stop. if the id pin is floated the last rxcmd from the USB3370 will remain on the bus after dir is de-asserted and the USB3370 will take this in as a txcmd. a link should be designed to hav e the default por state of the stp output high and the data bus tri-stated. the USB3370 has weak pull-downs on the data bus to prevent thes e inputs from floating when not driven. these resistors are only used to prevent the ulpi inte rface from floating during events when th e link ulpi pins may be tri-stated. the strength of the pull down resistors can be found in table 4-4 . the pull downs are not strong enough to pull the data bus low after a ulpi rxcmd, the link must drive the data bus to idle after dir is de-asserted. in some cases, a link may be software configured and not have control of its stp pin until after the phy has started. in this case, the USB3370 has in internal pull-up on the stp input pad which will pull stp high while the link?s stp output is tri-stated. the stp pull-up resistor is enabled on por and can be disabled by setting the interfaceprotectdis- able bit 7 of the interface control register. the stp pull-up resistor will pull-up the link?s stp input high until the link configures and drives stp high. after the link completes its start-up, stp can be synchronously driven low. a link design which drives stp high during por can disable the pull-up resistor on stp by setting interfaceprotect- disable bit to 1. a motivation for this is to reduce the suspend current. in low power mode, stp is held low, which would draw current through the pull-up resistor on stp . 6.5.4.2 warm reset designers should also consider the case of a warm restar t of a link with a phy in low power mode. after the phy enters low power mode, dir is asserted and the clock is stopped. the USB3370 looks for stp to be asserted to re- start the clock and then resume normal synchronous operation. should the USB3370 be suspended in low power mode, and th e link receives a hardware reset, the phy must be able to recover from low power mode and start its clock. if the link asserts stp on reset, the phy will exit low power mode and start its clock. if the link does not assert stp on reset, the interface protection pull-up can be used. when the link is reset, its stp output will tri-state and t he pull-up resistor will pull stp high, signaling the phy to restart its clock. 6.5.5 minimizing current in low power mode in order to minimize the suspend current in low power m ode, the vbus and id comparators can be disabled to reduce suspend current. in low power mode, the vbusvld and sessend comparators are not needed and can be disabled by clearing the associated bits in both the usb interrupt enable rising and usb interrupt enable falling registers. by dis- abling the interrupt in both the rise and fall register s, the sessend and vbusvld comparators are turned off. the idfloatrise and idfloatfall bits in carkit interrupt enable register should also be disabled if they were set. when exiting low power mode, the link should immediately re-enable t he vbusvld and sessend comparators if host or otg func- tionality is required. in addition to disabling the otg comparators in low power mo de, the link may choose to disable the interface protect circuit. by setting the interfaceprotectdisable bit high in the interface control register, the link can disable the pull-up resistor on stp . when resetb is low the interface protect circuit will be disabled. 6.6 full speed/low speed serial modes the USB3370 includes two serial modes to support legacy lin ks which use either the 3pin or 6pin serial format. to enter either serial mode, the link will need to write a 1 to the 6-pin fslsserialmode or the 3-pin fslsserialmode bits in the interface control register. serial mode may be used to conser ve power when attached to a device that is not capable of operating in hi-speed. the serial modes are entered in the same manner as the en try into low power mode. the link writes the interface control register bit for the specific serial mode. the USB3370 will assert dir and shut off the clock after at least five clock cycles. then the data bus goes to the format of the serial mode selected. before entering serial mode the link must set the ulpi transceiver to the appropriate mode as defined in ta b l e 5 - 1 . in ulpi clock output mode, the phy w ill shut off the 60mhz clock to conserve power. should the link need the 60mhz clock to continue during the serial mode of operation, the clocksuspendm bit[3] of the interface control register should be set before entering a serial mode. if set, the 60 mhz clock will be present during serial modes.
USB3370 ds00001915b-page 48 ? 2012 - 2015 microchip technology inc. in serial mode, interrupts are possible from unmasked source s. the state of each interrupt source is sampled prior to the assertion of dir and this is compared against the asynchronous level from interrupt source. exiting the serial modes is the same as ex iting low power mode. the link must assert stp to signal the phy to exit serial mode. when the phy can accept a command, dir is de-asserted and the phy will wait until the link de-asserts stp to resume synchronous ulpi operation. the resetb pin can also be pulsed low to reset the USB3370 and return it to synchronous mode. 6.6.1 3-pin fs/ls serial mode three pin serial mode utilizes the data bus pins for the serial functions shown in ta b l e 6 - 8 . 6.6.2 6-pin fs/ls serial mode six pin serial mode utilizes the data bus pins for the serial functions shown in ta b l e 6 - 9 . 6.7 carkit mode the USB3370 includes carkit mode to support a usb uart mode. by entering carkit mode, the USB3370 cu rrent drain is minimized. the intern al pll is disabled and the 60mhz ulpi clkout will be stopped to conserve power by default. the link may configure the 60mhz clock to continue by setting the clocksuspendm bit of the interface control register before entering carkit m ode. if set, the 60 mhz clock will con- tinue during the carkit mode of operation. in carkit mode, interrupts are possibl e if they have been enabled in the carkit interrupt enable register. the state of each interrupt source is sampled prior to the assertion of dir and this is compared against the asynchronous level from interrupt source. in carkit mode, the linestate si gnals are not available per the ulpi specification. the ulpi interface is redefined to th e following when carkit mode is entered. table 6-8: pin definition s in 3 pin serial mode signal connected to direction description tx_enable data[0] in active high transmit enable. data data[1] i/o tx differential data on dp/dm when tx_enable is high. rx differential data from dp/dm when tx_enable is low. se0 data[2] i/o tx se0 on dp/dm when tx_enable is high. rx se0_b from dp/dm when tx_enable is low. interrupt data[3] out asserted when any unmasked interrupt occurs. active high. reserved data[7:4] out driven low. table 6-9: pin definition s in 6 pin serial mode signal connected to direction description tx_enable data[0] in active high transmit enable. tx_data data[1] in tx differential data on dp/dm when tx_enable is high. tx_se0 data[2] in tx se0 on dp/dm when tx_enable is high. interrupt data[3] out asserted when any unmasked interrupt occurs. active high. rx_dp data[4] out single ended receive data on dp. rx_dm data[5] out single ended receive data on dm. rx_rcv data[6] out differential receive data from dp and dm. reserved data[7] out driven low.
? 2012 - 2015 microchip technology inc. ds00001915b-page 49 USB3370 exiting carkit mode is the same as exiting low power mode as described in section 6.5.2 . the link must assert stp to signal the phy to exit serial mo de. when the phy can accept a command, dir is de-asserted and the phy will wait until the link de-asserts stp to resume synchronous ulpi operation. the resetb pin can also be pulsed low to reset the USB3370 and return it to synchronous mode. 6.7.1 entering usb uart mode the USB3370 can be placed into uart mode by first setting the txden and rxden bits in the carkit control register. then the link can set the carkitmode bit in the interface control register. the txden and rxden bits must be written before the carkitmode bit. after the carkitmode bit is set, the ulpi interface will become redefined as described in ta b l e 6 - 1 0 , and the USB3370 will transmit data through the data[0] to dm of the usb connector and receive data on dp and pass the information the link on data[1] . when entering uart mode, the regulat or output will automatically switch to the value configured by the uart regout- put bits in the usb io & power management register and the r cd pull-up resistors will be applied internally to dp and dm . this will hold the uart in its default operating state. while in uart mode, the transmit edge rates can be set to either the full speed usb or low speed usb edge rates by using the xcvrselect[1:0] bits in the function control register. 6.8 rid converter operation the rid converter is designed to read the value of the id resistance to ground and report back its value through the ulpi interface. when a resistor to ground is applied to the id pin the state of the idgnd comparator will change from a 1 to a 0 as described in section 5.7.1 . if the USB3370 is in ulpi mode, an rxcmd will be generated with bit 6 low. if the USB3370 is in low power mode (or one of the other non-ulpi modes), the data[3] interrupt signal will go high. after the USB3370 has detected the change of state on the id pin, the rid converter can be used to determine the value of id resistance. to start a id resistance measurement, the ridconversionstart bit is set in the vendor rid conversion register. table 6-10: pin definitions in carkit mode signal connected to direction description txd data[0] in uart txd signal that is routed to the dm pin if the txden is set in the carkit control register. rxd data[1] out uart rxd signal that is routed to the dp pin if the rxden bit is set in the carkit control register. reserved data[2] out driven low ( carkitdatamc = 0, default) in tri-state (carkitdatamc = 1) int data[3] out asserted when any unmasked interrupt occurs. active high. reserved data[4:7] out driven low. table 6-11: ulpi register progra mming example to enter uart mode r/w address (hex) value (hex) description result w 04 49 configure non-driving mode select fs transmit edge rates opmode =01 xcvrselect =01 w 39 00 set regulator to 3.3v uart regoutput =00 w 19 0c enable uart connections rxden =1 txden =1 w 07 04 enable carkit mode carkitmode =1
USB3370 ds00001915b-page 50 ? 2012 - 2015 microchip technology inc. the link can use one of two methods to determine when t he rid conversion is complete. one method is polling the ridconversionstart bit as described in section 7.1.3.3 . the preferred method is to set the ridinten bit in the vendor rid conversion register. when ridinten is set, an rxcmd will be generated after the rid conversion is complete. as described in table 6-3 , the alt_int bit of the rxcmd will be set. after the rid conversion is complete, the link can read ridvalue from the vendor rid conversion register.
? 2012 - 2015 microchip technology inc. ds00001915b-page 51 USB3370 7.0 ulpi register map 7.1 ulpi register array the USB3370 phy implements all of the ulpi registers deta iled in the ulpi revision 1.1 specification. the complete USB3370 ulpi register set is shown in table 7-1 . all registers are 8 bits. this tabl e also includes the default state of each register upon por or de-assertion of resetb , as described in section 5.6.2 . the reset bit in the function con- trol register does not reset the bits of the ulpi register arra y. the link should not read or write to any registers not listed in this table. the USB3370 supports extended register access. the immediat e register set (00-3fh) can be accessed through either a immediate address or an extended register address. note 7-1 dynamically updates to reflect current status of interrupt sources. table 7-1: ulpi register map register name default state address (6bit) read write set clear vendor id low 24h00h--- vendor id high 04h01h--- product id low 0dh02h--- product id high 00h03h--- function control 41h 04-06h 04h 05h 06h interface control 00h 07-09h 07h 08h 09h otg control 06h 0a-0ch 0ah 0bh 0ch usb interrupt enable rising 1fh 0d-0fh 0dh 0eh 0fh usb interrupt enable falling 1fh 10-12h 10h 11h 12h usb interrupt status ( note 7-1 ) 00h13h--- usb interrupt latch 00h14h--- debug 00h15h--- scratch register 00h 16-18h 16h 17h 18h carkit control 00h 19-1bh 19h 1ah 1bh reserved 00h 1ch carkit interrupt enable 00h 1d-1fh 1dh 1eh 1fh carkit interrupt status 00h20h--- carkit interrupt latch 00h21h--- reserved 00h 22-30h hs compensation register 00h 31h 31h - - usb-if charger detection 00h 32h 32h - - reserved 00h 33-35h vendor rid conversion 00h 36-38h 36h 37h 38h usb io & power management 04h 39-3bh 39h 3ah 3bh reserved 00h 3c-3fh
USB3370 ds00001915b-page 52 ? 2012 - 2015 microchip technology inc. 7.1.1 ulpi register set the following registers are used for the ulpi interface. 7.1.1.1 vendor id low address = 00h (read only) 7.1.1.2 vendor id high address = 01h (read only) 7.1.1.3 product id low address = 02h (read only) 7.1.1.4 product id high address = 03h (read only) 7.1.1.5 function control address = 04-06h (read), 04h (w rite), 05h (set), 06h (clear) field name bit access default description vendor id low 7:0 rd 24h mchp vendor id field name bit access default description vendor id high 7:0 rd 04h mchp vendor id field name bit access default description product id low 7:0 rd 0dh mchp product id field name bit access default description product id high 7:0 rd 00h mchp product id field name bit access default description xcvrselect[1:0] 1:0 rd/w/s/c 01b selects the required transceiver speed. 00b: enables hs transceiver 01b: enables fs transceiver 10b: enables ls transceiver 11b: enables fs transceiver for ls packets (fs preamble automatically pre-pended) termselect 2 rd/w/s/c 0b controls the dp and dm termination depending on xcvrselect , opmode , dppulldown , and dmpulldown . the dp and dm termination is detailed in ta b l e 5 - 1 . opmode[1:0] 4:3 rd/w/s/c 00b selects the required bit encoding style during transmit. 00b: normal operation 01b: non-driving 10b: disable bit-stuff and nrzi encoding 11b: reserved reset 5 rd/w/s/c 0b active high transceiver reset. this reset does not reset the ulpi interface or register set. automatically clears after reset is complete.
? 2012 - 2015 microchip technology inc. ds00001915b-page 53 USB3370 7.1.1.6 interface control address = 07-09h (read), 07h (w rite), 08h (set), 09h (clear) 7.1.1.7 otg control address = 0a-0ch (read), 0ah (write), 0bh (set), 0ch (clear) suspendm 6 rd/w/s/c 1b active low phy suspend. when cleared the phy will enter low power mode as detailed in section 6.5 . automatically set when exiting low power mode. lpm enable 7 rd/w/s/c 0b when enabled the pll start-up time is shortened to allow fast start-up for lpm. the reduced pll start-up time is achieved by bypassing the vco process compensation which was done on initial start-up. field name bit access default description 6-pin fslsserialmode 0 rd/w/s/c 0b when asserted the ulpi interface is redefined to the 6-pin serial mode. the phy will automatically clear this bit when exiting serial mode. 3-pin fslsserialmode 1 rd/w/s/c 0b when asserted the ulpi interface is redefined to the 3-pin serial mode. the phy will automatically clear this bit when exiting serial mode. carkitmode 2 rd/w/s/c 0b when asserted the ulpi interface is redefined to the carkit interface. the phy will automatically clear this bit when exiting carkit mode. clocksuspendm 3 rd/w/s/c 0b enables link to turn on 60mhz clkout in serial mode or carkit mode. 0b: disable clock in serial or carkit mode. 1b: enable clock in serial or carkit mode. autoresume 4 rd/w/s/c 0b only applicable in host mode. enables the phy to automatically transmit resume signaling. this function is detailed in section 6.4.1.4 . indicatorcomplement 5 rd/w/s/c 0b inverts the extvbus signal. this function is detailed in section 5.7.2 . indicatorpassthru 6 rd/w/s/c 0b disables and?ing the internal vbus comparator with the extvbus signal when asserted. this function is detailed in section 5.7.2 . interfaceprotectdisable 7 rd/w/s/c 0b used to disable the integrated stp pull-up resistor used for interface protection. this function is detailed in section 6.5.4 . field name bit access default description idpullup 0 rd/w/s/c 0b connects a 100k ? pull-up resistor from the id pin to vdd33 0b: disables the pull-up resistor 1b: enables the pull-up resistor dppulldown 1 rd/w/s/c 1b enables the 15k ohm pull-down resistor on dp . 0b: pull-down resistor not connected 1b: pull-down resistor connected dmpulldown 2 rd/w/s/c 1b enables the 15k ohm pull-down resistor on dm . 0b: pull-down resistor not connected 1b: pull-down resistor connected field name bit access default description
USB3370 ds00001915b-page 54 ? 2012 - 2015 microchip technology inc. 7.1.1.8 usb interrupt enable rising address = 0d-0fh (read), 0dh (w rite), 0eh (set), 0fh (clear) 7.1.1.9 usb interrupt enable falling address = 10-12h (read), 10h (wri te), 11h (set), 12h (clear) dischrgvbus 3 rd/w/s/c 0b this bit is only used during srp. connects a resistor from vbus to ground to discharge vbus . 0b: disconnect resistor from vbus to ground 1b: connect resistor from vbus to ground chrgvbus 4 rd/w/s/c 0b this bit is only used during srp. connects a resistor from vbus to vdd33 to charge vbus above the sessvalid threshold. 0b: disconnect resistor from vbus to vdd33 1b: connect resistor from vbus to vdd33 drvvbus 5 rd/w/s/c 0b enables external 5 volt supply to drive 5 volts on vbus. this signal is or?ed with drvvbusexternal . 0b: do not drive vbus, cpen_n tri-stated. 1b: drive vbus, cpen_n driven low. drvvbusexternal 6 rd/w/s/c 0b enables external 5 volt supply to drive 5 volts on vbus. this signal is or?ed with drvvbus . 0b: do not drive vbus, cpen_n tri-stated. 1b: drive vbus, cpen_n driven low. useexternalvbus indicator 7 rd/w/s/c 0b tells the phy to use an external vbus over-current or voltage indicator. this function is detailed in section 5.7.2 . 0b: use the internal vbusvalid comparator 1b: use the extvbus input as for vbusvalid signal. field name bit access default description hostdisconnect rise 0 rd/w/s/c 1b generate an interrupt event notification when hostdisconnect changes from low to high. applicable only in host mode. vbusvalid rise 1 rd/w/s/c 1b generate an interrupt event notification when vbusvalid changes from low to high. sessvalid rise 2 rd/w/s/c 1b generate an interrupt event notification when sessvalid changes from low to high. sessend rise 3 rd/w/s/c 1b generate an interrupt event notification when sessend changes from low to high. idgnd rise 4 rd/w/s/c 1b generate an interrupt event notification when idgnd changes from low to high. reserved 7:5 rd 0h read only, 0. field name bit access default description hostdisconnect fall 0 rd/w/s/c 1b generate an interrupt event notification when hostdisconnect changes from high to low. applicable only in host mode. vbusvalid fall 1 rd/w/s/c 1b generate an interrupt event notification when vbusvalid changes from high to low. sessvalid fall 2 rd/w/s/c 1b generate an interrupt event notification when sessvalid changes from high to low. sessend fall 3 rd/w/s/c 1b generate an interrupt event notification when sessend changes from high to low. field name bit access default description
? 2012 - 2015 microchip technology inc. ds00001915b-page 55 USB3370 7.1.1.10 usb interrupt status address = 13h (read only) this register dynamically updates to reflect current status of interrupt sources. 7.1.1.11 usb interrupt latch address = 14h (read only with auto clear) note 7-2 rd: read only with auto clear. idgnd fall 4 rd/w/s/c 1b generate an interrupt event notification when idgnd changes from high to low. reserved 7:5 rd 0h read only, 0. field name bit access default description hostdisconnect 0 rd (read only) 0b current value of the utmi+ hs hostdisconnect output. applicable only in host mode. vbusvalid 1 0b current value of the utmi+ vbusvalid output. if vbusvalid rise and vbusvalid fall are set this register will read 0. sessvalid 2 0b current value of the utmi+ sessvalid output. this register will always read the current status of the session valid comparator regardless of the sessvalid rise and sessvalid fall settings. sessend 3 0b current value of the utmi+ sessend output. if sessend rise and sessend fall are set this register will read 0. idgnd 4 0b current value of the utmi+ idgnd output. reserved 7:5 0h read only, 0. note: the default value is only valid after por. when the regi ster is read it will match the current status of the comparators at the moment the register is read. field name bit access default description hostdisconnect latch 0 rd ( note 7-2 ) 0b set to 1b by the phy when an unmasked event occurs on hostdisconnect. cleared when this register is read. applicable only in host mode. vbusvalid latch 1 0b set to 1b by the phy when an unmasked event occurs on vbusvalid. cleared when this register is read. sessvalid latch 2 0b set to 1b by the phy when an unmasked event occurs on sessvalid. cleared when this register is read. sessend latch 3 0b set to 1b by the phy when an unmasked event occurs on sessend. cleared when this register is read. idgnd latch 4 0b set to 1b by the phy when an unmasked event occurs on idgnd. cleared when this register is read. reserved 7:5 rd 0h read only, 0. field name bit access default description
USB3370 ds00001915b-page 56 ? 2012 - 2015 microchip technology inc. 7.1.1.12 debug address = 15h (read only) 7.1.1.13 scratch register address = 16-18h (read), 16h (w rite), 17h (set), 18h (clear) 7.1.2 carkit control registers the following registers are used to se t-up and enable the usb uart functions. 7.1.2.1 carkit control address = 19-1bh (read), 19h (w rite), 1ah (set), 1bh (clear) this register is used to program the USB3370 into and out of the carkit mode. when entering the uart mode the link must first set the desired txden and the rxden bits and then transition to carkit mode by setting the carkitmode bit in the interface control register. when rxden is not set then the data[1] pin is held to a logic high. 7.1.2.2 carkit interrupt enable address = 1d-1fh (read), 1dh (w rite), 1eh (set), 1fh (clear) field name bit access default description linestate[1:0] 1:0 rd 00b contains the current value of linestate[1:0]. reserved 7:2 rd 000000b read only, 0. field name bit access default description scratch 7:0 rd/w/s/c 00h empty regi ster byte for testing purposes. software can read, write, set, and clear this register and the phy functionality will not be affected. field name bit access default description carkitpwr 0 rd 0b read only, 0. idgnddrv 1 rd/w/s/c 0b drives id pin to ground txden 2 rd/w/s/c 0b connects uart txd ( data[0] ) to dm rxden 3 rd/w/s/c 0b connects uart rxd ( data[1] ) to dp reserved 4 rd/w/s/c 0b reserved 5 rd/w/s/c 0b reserved 6 rd/w/s/c 0b carkitdatamc 7 rd/w/s/c 0b when set the upli data[2] pin is changed from a driven 0 to tri-state, w hen carkit mode is entered. field name bit access default description idfloatrise 0 rd/w/s/c 0b when enabled an interrupt will be generated on the alt_int of the rxcmd byte when the id pin transitions from non-floating to floating. the idpullup bit in the otg control register should be set. idfloatfall 1 rd/w/s/c 0b when enabled an interrupt will be generated on the alt_int of the rxcmd byte when the id pin transitions from floating to non-floating. the idpullup bit in the otg control register should be set. vdatdetinten 2 rd/w/s/c 0b when enabled an interrupt will be generated on the alt_int of the rxcmd byte when the v dat_det comparator changes state.
? 2012 - 2015 microchip technology inc. ds00001915b-page 57 USB3370 7.1.2.3 carkit interrupt status address = 20h (read only) cardprise 3 rd 0b not implemented. reads as 0b. cardpfall 4 rd 0b not implemented. reads as 0b. ridinten 5 rd/w/s/c 0b when enabled an interrupt will be generated on the alt_int of the rxcmd byte when ridconversiondone bit is asserted. note: this register bit is or?ed with the ridinten bit of the vendor rid conversion register described in section 7.1.3.3 . reserved 6 rd 0b read only, 0. reserved 7 rd 0b read only, 0. field name bit access default description idfloat 0 rd 0b asserted when the id pin is floating. idpullup must be enabled. vdatdet 1rd 0bv dat_det comparator output 0b: no voltage is detected on dp 1b: voltage detected on dp , idatsinken must be set to 1. note: vdatdet can also be read from the usb-if charger detection register described in section 7.1.3.3 . cardp 2 rd 0b not implemented. reads as 0b. ridvalue 5:3 rd 000b conversion value of rid resistor 000: 0 ohms 001: 75 ohms 010: 102k ohms 011: 200k ohms 100: reserved 101: id floating 111: error note: ridvalue can also be read from the vendor rid conversion register described in section 7.1.3.3 . ridconversiondone 6 rd 0b automatically asserted by the USB3370 when the rid conversion is finished. the conversion will take 282us. this bit will auto clear when the ridvalue is read from the rid conversion register. reading the ridvalue from the carkit interrupt status register will not clear either ridconversiondone status bit. note: ridconversiondone can also be read from the vendor rid conversion register described in section 7.1.3.3 . reserved 7 rd 0b read only, 0. field name bit access default description
USB3370 ds00001915b-page 58 ? 2012 - 2015 microchip technology inc. 7.1.2.4 carkit interrupt latch address = 21h (read only with auto-clear) note 7-3 rd: read only with auto clear 7.1.3 vendor register access the vendor specific registers include the range from 30h to 3f h. these can be accessed by the ulpi immediate register read / write. 7.1.3.1 hs compensation register address = 31h (read / write) the USB3370 is designed to meet the usb specifications and requirements when the dp and dm signals are properly designed on the pcb. the dp and dm tr ace impedance should be 45ohm single ended and 90ohm differential. in cases where the dp and dm traces are not able to meet these requirements the hs compensation register can be used to compensate for the losses in signal amplitude. field name bit access default description idfloat latch 0rd ( note 7- 3 ) 0b asserted if the state of the id pin changes from non- floating to floating while the idfloatrise bit is enabled or if the state of the id pin changes from floating to non-floating while the idfloatfall bit is enabled. vdatdet latch 1rd 0bif vdatdetinten is set and the vdatdet bit changes state, this bit will be asserted. cardp latch 2 rd 0b not implemented. reads as 0b. ridconversionlatch 3rd ( note 7-3 ) 0b if ridinten is set and the state of the ridconversiondone bit changes from a 0 to 1 this bit will be asserted. reserved 7:4 rd 0000b read only, 0. field name bit access default description varisense 1:0 rd/w 00b used to lower the threshold of the squelch detector. 00: 100% (default) 01: 83% 10: 66.7% 11: 50% reserved 2 rd 0b read only, 0. reserved 3 rd 0b read only, 0. phyboost 6:4 rd/w 000b used to change the output voltage of the hi-speed transmitter 000: nominal 001: +3.7% 010: +7.4% 011: +11.0% 100: +14.7% 101: +18.3% 110: +22.0% 111: +25.7% reserved 7 rd 0b read only, 0.
? 2012 - 2015 microchip technology inc. ds00001915b-page 59 USB3370 7.1.3.2 usb-if charger detection address = 32h (read / write) 7.1.3.3 vendor rid conversion address = 36-38h (read), 36h (w rite), 37h (set), 38h (clear) field name bit access default description vdatsrcen 0rd/w 0v dat_src voltage enable 0b: disabled 1b: enabled idatsinken 1rd/w 0i dat_sink current sink and v dat_det comparator enable 0b: disabled, v dat_det = 0. 1b: enabled contactdetecten 2rd/w 0i dp_src enable 0b: disabled 1b: enabled hostchrgen 3 rd/w 0 enable charging host port mode. 0b: portable device 1b: charging host port. when the charging host port bit is set the connections of v dat_src , i dat_sink , i dp_src , and v dat_det are reversed between dp and dm . vdatdet 4rd 0v dat_det comparator output. idatsinken must be set to 1 to enable the comparator. 0b: no voltage is detected on dp or linestate[1:0] is not equal to 00b. 1b: voltage detected on dp , and linestate[1:0] = 00b. note: vdatdet can also be read from the carkit interrupt status register described in section 7.1.2.3 . reserved 5-7 rd read only, 0. note: the charger detection should be turned off before beginning usb operation. usb-if charger detection bits 2:0 should be set to 000b. field name bit access default description ridvalue 2:0 rd/w 000b conversion value of rid resistor 000: 0 ohms 001: 75 ohms 010: 100k ohms 011: 200k ohms 100: 440k ohms 101: id floating 111: error note: ridvalue can also be read from the carkit interrupt status register. ridconversiondone 3rd ( note 7- 4 ) 0b automatically asserted by the USB3370 when the rid conversion is finished. the conversion will take 282us. this bit will auto clear when the ridvalue is read from the rid conversion register. reading the ridvalue from the carkit interrupt status register will not clear either ridconversiondone status bit. note: ridconversiondone can also be read from the carkit interrupt status register.
USB3370 ds00001915b-page 60 ? 2012 - 2015 microchip technology inc. note 7-4 rd: read only with auto clear. 7.1.3.4 usb io & power management address = 39-3bh (read), 39h (w rite), 3ah (set), 3bh (clear) ridconversionstart 4 rd/w/s/c 0b when this bit is asserted either through a register write or set, the rid converter will read the value of the id resistor. when the conversion is complete this bit will auto clear. reserved 5 rd/w/s/c 0b this bit must remain at 0. ridinten 6 rd/w/s/c 0b when enabled an interrupt will be generated on the alt_int of the rxcmd byte when ridconversiondone bit is asserted. note: this register bit is or?ed with the ridinten bit of the carkit interrupt status register. reserved 7 rd 0b read only, 0. field name bit access default description reserved 0 rd/w/s/c 0b read only, 0. swapdp/dm 1 rd/w/s/c 0b when asserted, the dp and dm pins of the usb transceiver are swapped. this bit can be used to prevent crossing the dp/dm traces on the board. in uart mode, it swaps the routing to the dp and dm pins. uart regoutput 3:2 rd/w/s/c 01b controls th e output voltage of the vbat to vdd33 regulator in uart mode. when the phy is switched from usb mode to uart mode regulator output will automatically change to the value specified in this register when txden is asserted. 00: 3.3v 01: 3.0v (default) 10: 2.75v 11: 2.5v chargerpullupendp 4 rd/w/s/c 0b enables the r cd pull-up resistor on the dp pin. (the pull-up is automatically enabled in uart mode) chargerpullupendm 5 rd/w/s/c 0b enables the r cd pull-up resistor on the dm pin. (the pull-up is automatically enabled in uart mode) usb regoutput 7:6 rd/w/s/c 00b controls th e output voltage of the vbat to vdd33 regulator in usb mode. when the phy is in synchronous mode, serial mode, or low power mode, the regulator output will be t he value specified in this register. 00: 3.3v (default) 01: 3.0v 10: 2.75v 11: 2.5v field name bit access default description
? 2012 - 2015 microchip technology inc. ds00001915b-page 61 USB3370 8.0 application notes 8.1 application diagrams the USB3370 requires few external components as shown in the application diagrams. the usb 2.0 specification restricts the voltage at the vbus pin to a maximum value of 5.25v. in some applications, the voltage will exceed this limit, so the USB3370 provides an integrated over voltage protection circuit. the over voltage protection circuit works with an external resistor (r vbus ) to lower the voltage at the vbus pin. table 8-1: component values in application diagrams reference designator value description notes c out see ta b l e 4 - 1 0 bypass capacitor to ground (<1 esr) for regulator stability. place as close as possible to the phy. c vbus see ta b l e 8 - 2 capacitor to ground required by the usb specification. microchip recommends <1 esr. place near the usb connector. c byp system dependent. bypass capacitor to ground. typical values used are 0.1 or 0.01 f. place as close as possible to the phy. c dc_load system dependent. the usb connector housing may be ac- coupled to the device ground. industry convention is to ground only the host side of the cable shield. r vbus 1k or 20k series resistor to work with internal over voltage protection. see section 5.7.3.4 for information regarding power dissipation. r bias 10k (1%) series resistor to establish reference voltage. see section 5.3 for information regarding power dissipation. table 8-2: capacitance values at vbus of usb connector mode min value max value host 120 f device 1 f10 f otg 1 f6.5 f
USB3370 ds00001915b-page 62 ? 2012 - 2015 microchip technology inc. figure 8-1: USB3370 application diagra m (host configured for ulpi clock input mode) 5v vbus vbat vdd33 id dm dp gnd usb receptacle dm dp id shield gnd vbus c out 3.0-5.5v supply c byp r vbus the capacitor c vbus must be installed on this side of r vbus . c vbus r vbus must be installed to enable overvoltage protection of the vbus pin. cpen_n link controller dir nxt stp clkin data7 data6 data5 data4 data3 data2 data0 data1 resetb r bias dir nxt stp clkout data7 data6 data5 data4 data3 data2 data0 data1 resetb rbias vdd18 c out vddio c byp vddio supply c load resonator crystal and caps - or - refclk xo for host applications (non- otg), the id pin should be connected to gnd. extvbus vbus switch out en in fault
? 2012 - 2015 microchip technology inc. ds00001915b-page 63 USB3370 figure 8-2: USB3370 application diagra m (device configured for ulpi clock output mode) 3.0-5.5v supply r vbus must be installed to enable overvoltage protection of the vbus pin. c dc_block the capacitor c vbus must be installed on this side of r vbus . link controller dir nxt stp clkin data7 data6 data5 data4 data3 data2 data0 data1 resetb refclk usb receptacle dm dp vbus shield gnd r bias dir nxt stp clkout data7 data6 data5 data4 data3 data2 data0 data1 resetb vdd33 dm dp gnd c out c out c byp r vbus c vbus vddio c byp vddio supply cpen_n xo extvbus id refclk vbus vdd18 rbias vbat
USB3370 ds00001915b-page 64 ? 2012 - 2015 microchip technology inc. 8.2 usb charger detection the USB3370 provides the hardware described in the usb ba ttery charging specification. microchip provides an appli- cation note which describes how to use th e USB3370 in a battery charging application. 8.3 reference designs microchip has generated reference designs for connecting the USB3370 to socs with a ulpi port. please contact the microchip sales office for more details. 8.4 esd performance the USB3370 is protected from esd strikes. by eliminating t he requirement for external esd protection devices, board space is conserved, and the board m anufacturer is enabled to reduce cost. the advanced esd structures integrated into the USB3370 protect the device whether or not it is powered up. 8.4.1 human body model (hbm) performance hbm testing verifies the ability to withs tand the esd strikes like t hose that occur during handling and manufacturing, and is done without power applied to the ic. to pass the tes t, the device must have no ch ange in operation or perfor- mance due to the event. the USB3370 hbm performance is detailed in ta b l e 4 - 1 2 . figure 8-3: USB3370 application diagra m (host configured for ulpi clock output mode) 3.0-5.5v supply r vbus must be installed to enable overvoltage protection of the vbus pin. c dc_block the capacitor c vbus must be installed on this side of r vbus . link controller dir nxt stp clkin data7 data6 data5 data4 data3 data2 data0 data1 resetb refclk usb receptacle dm dp vbus shield gnd r bias dir nxt stp clkout data7 data6 data5 data4 data3 data2 data0 data1 resetb vdd33 dm dp gnd c out c out c byp r vbus c vbus vddio c byp vddio supply cpen_n xo extvbus id refclk vbus vbus switch out en in 5v rbias vdd18 vbat
? 2012 - 2015 microchip technology inc. ds00001915b-page 65 USB3370 8.4.2 en/iec 61000-4-2 performance the en/iec 61000-4-2 esd spec ification is an international standard that addresses system-level immunity to esd strikes while the end equipment is operational. in contra st, the hbm esd tests are performed at the device level with the device powered down. microchip contracts with independent la boratories to test the USB3370 to en/iec 61000-4-2 in a working system. reports are available upon request. please contact your micr ochip representative, and request information on 3rd party esd test results. the reports show t hat systems designed with the USB3370 c an safely provide the esd performance shown in ta b l e 4 - 1 2 without additional board level protection. in addition to defining the esd tests, en/iec 61000-4-2 also categorizes the impact to equipment operation when the strike occurs (esd result classification). the USB3370 maintains an esd result classification 1 or 2 when subjected to an en/iec 61000-4-2 (level 4) esd strike. both air discharge and contact discharge test techniques for applying stress conditio ns are defined by the en/iec 61000-4-2 esd document. 8.4.2.1 air discharge to perform this test, a charged electrode is moved close to t he system being tested until a spark is generated. this test is difficult to reproduce because the discharge is influenced by such factors as humidity, the speed of approach of the electrode, and constructi on of the test equipment. 8.4.2.2 contact discharge the uncharged electrode first contacts the usb connector to pr epare this test, and then the probe tip is energized. this yields more repeatable results, and is the preferred test me thod. the independent test labor atories contracted by micro- chip provide test results for both types of discharge methods.
USB3370 ds00001915b-page 66 ? 2012 - 2015 microchip technology inc. 9.0 package outline figure 9-1: USB3370 32-pin qf n, 5x5mm body , 0.5mm pitch note: for the most current package drawings, see the microchip packaging specification at http://www.microchip.com/packaging
? 2012 - 2015 microchip technology inc. ds00001915b-page 67 USB3370 figure 9-1: USB3370 32-pin qfn, 5x 5mm body, 0.5mm pi tch (continued) note: for the most current package drawings, see the microchip packaging specification at http://www.microchip.com/packaging
USB3370 ds00001915b-page 68 ? 2012 - 2015 microchip technology inc. figure 9-2: 32qfn, 5x5 tape and reel
? 2012 - 2015 microchip technology inc. ds00001915b-page 69 USB3370 figure 9-3: 32qfn, 5x5 reel dimensions
USB3370 ds00001915b-page 70 ? 2012 - 2015 microchip technology inc. figure 9-4: 32qfn tape length and part quantity
? 2012 - 2015 microchip technology inc. ds00001915b-page 71 USB3370 appendix a: data sheet revision history table a-1: customer revision history revision level & date secti on/figure/entr y correction ds00001915b (05-12-15) document features adde d to external reference clock operation bullet: ?19.2mhz reference clock? needed product identification system page ?192mhz? changed to ?19.2mhz? ds00001915a (04-06-15) replaces previous smsc version rev. 1.0 (10-08-12) rev. 1.0 (10-08-12) initial data sheet release
USB3370 ds00001915b-page 72 ? 2012 - 2015 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep custom ers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://www.microchip.com/support
? 2012 - 2015 microchip technology inc. ds00001915b-page 73 USB3370 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . part no. xxx package device device: USB3370b package: ezk = 32-pin qfn, 19.2mhz refclk frequency tape and reel option: tr = tape and reel (1) example: USB3370b-ezk-tr = 32-pin qfn rohs compliant package tape & reel [x] tape and reel option - note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the dev ice package. check with your microchip sa les office for package availability with the tape and reel option. reel size is 5,000. -
USB3370 ds00001915b-page 74 ? 2012 - 2015 microchip technology inc. information contained in this publication regarding device applic ations and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip make s no representations or warranties of any kind whether ex press or implied, written or oral, statutory or otherwise, related to the information, including bu t not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is ent irely at the buyer?s risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashf lex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technolog y incorporated in the u.s.a. and other countries. the embedded control solutions company and mtou ch are registered trademarks of microchi p technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem. net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pi ctail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, view span, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012 - 2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 9781632773715 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the se curity of their code. c ode protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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